AN1849 Motorola / Freescale Semiconductor, AN1849 Datasheet
AN1849
Related parts for AN1849
AN1849 Summary of contents
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... To locate any published errata or updates for this document, refer to the website at http://www.motorola.com/semiconductors. This document contains information on a new product under development by Motorola. Motorola reserves the right to change or discontinue this product without notice. © Motorola, Inc., 2000. All rights reserved. Order Number: AN1849/D Rev. 0.8, 8/2000 Page 2 3 ...
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Overview The MPC107 is the newest generation of the PowerPC PCI/Memory controller family. The MPC107 is upwardly compatible with the MPC106 at a software level, preserves all the essential hardware features of the MPC106, and adds many new features, ...
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In general, designers who are familiar with the MPC106 will find that the MPC107 increases performance, eases design effort, and decreases overall board space. Designers new to the PowerPC family will find that the MPC107 supplies almost all of the ...
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This might require, for example, that large I/O system need buffering, or provide isolate address and control signal decoding in an FPGA or PAL. 1.4 ...
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This architecture uses a 33 MHz oscillator (or frequency synthesizer) to create the baseline PCI clock. The clock is distributed equally to the MPC107 core logic via PCI_SYNC_IN as well as the PCICLK pins of the other PCI devices. 1.4.2 ...
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The DLL in the MPC107 is similar to a PLL except that it divides the clock period into discrete intervals, in this case into 128 intervals. The DLL drives the SDRAM_SYNC_OUT signal and measures the number of intervals until the ...
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Table 2. Assumed PCB Electrical Parameters Trace Trace Impedance Height Width 0.005 0.005 Using these values, the only other data we need is: • Bus speed • Maximum memory trace length (clocks, controls, and data) • Capacitive loads (number and ...
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Using the information and equations listed above, we can see what sort of designs are possible, as shown in Table 4. Case “A” 2 Registered DIMMs DIMM type registered SDRAM type any PCB Trace 8.9 cm Co’ 0.91 pF/cm + ...
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SDRAM_SYNC_IN t CTQ=5.5 SDRAS, SDCAS MPC107 t OF=1.0 SDRAS, SDCAS SDRAM t LOOP=1.0 SDRAM_CLK0 at MPC107 t OF=1.0 SDRAM_CLK0 at SDRAM t CTQ=6.0 DQx at SDRAM DQx at MPC107 1.4.5 Expanding Memory Clocks ...
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MPC107 PCISYNC_IN OSC_IN Figure 6. Clock Expansion Using Zero-Delay Buffers Typical zero-delay buffers generate output clocks that are aligned to within 350ps of the input clock, which of course is not really zero, but can be adjusted to effectively zero ...
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SDRAM_SYNC_OUT t LOOP=1.0 sys_logic_clk SDRAM_SYNC_IN CPU_CLK0 at MPC107 t EXTRA=1.0 CPU_CLK0 at CPU Figure 7 shows how adding to the CPU_CLK traces (of delay t to communicate with PowerPC processors. 1.5 Memory Architecture The MPC107 contains a high-speed ...
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Memory Connections Connecting memory to the MPC107 is fairly straightforward, with the exception of the SDRAM clock signals, which have been discussed in section 1.4.3 on page 5. Otherwise, most signals on the MPC107 have the same name as ...
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The remaining memory connections can be connected from point-to-point. Table 6 shows a list of the interconnections between the MPC107 and a typical DIMM or SODIMM module. Note that, unlike most PowerPC buses, the memory buses (with the exception of ...
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... C and processing the results would be quite difficult. Once the debugger is running, the “meminfo” command can be automatically invoked to adjust the memory timing based on I data and the current memory bus clock speed. The source code for these modules are available on the web at http://www.mot.com/SPS/PowerPC/teksupport/tools ...
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ROM The MPC107 supports up to four ROM devices for code and data storage. Most embedded systems will need at least one ROM to boot from, and the remaining chip selects may be used as needed, including for general ...
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It may be necessary or desirable to add a buffer between the MPC107 signals and the address pins of the ROMs if more than the minimal 8-bit boot ROM is used (which has only one load and ...
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ROMs have particular (predefined) associations associated with the data bits. This is not only true with externally programmed ROMs, but programmable flash memories assign particular meanings to the data bits generally recommended to connect ...
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MPC7400 “A” Figure 11. Multiple MPC107-based System In systems where such an environment is not desired, or where the MPC107 is operating as a host, the active-high IDSEL pin must be tied low to prevent configuration cycles from being accepted. ...
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M66EN Figure 12. MPC107 PLL Dynamic Configuration The actual logic is highly dependant on the available and desired speeds of the PowerPC processor and the memory bus. If the PLL setting is fixed for a board (not changeable by the ...
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HRESET M66EN Figure 13. Automatic PCI Hold Time Adjustment This circuit pulls SDMA4 low if M66EN is high during reset, indicating 66 MHz PCI operation. This changes the default PCI hold time from “110” (2.9ns) to “000” (0.5 ...
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Table 10 shows the various supported voltages. Power Group Function VDD Internal (core) power BVDD Processor I/O power OVDD PCI/Other I/O power GVDD Memory I/O power LVDD PCI Clamp Voltage AVDD PLL/DLL filtered power LAVDD GND Ground, common The MPC107 ...
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VCC 3x 680uF low-ESR RC5051 VID(4:0) SWITCHES GND Figure 15. Shared MPC107 Power Supply While switching power supplies are more complicated and require more components than simple linear regulators, modern switching components are fairly easy to design with ...
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The PLL power connections should be kept as short as possible between the pin and the series resistor. The AVDD pin is near the exterior of the MPC107, and so its filter can be placed on either the top ...
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INTA 5 INT(0:4) Figure 17. MPC107 EPIC Interrupt Connections As shown in Figure 17, the EPIC gathers a variety of internal and external interrupts sources and forwards them to the processor. Interrupts can be masked, prioritized, and set to various ...
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INT0 INT15 Figure 18. MPC107 External Serial Multiplexer Block Diagram As shown in Figure 18, this logic does not make use of the S_RST signal. This signal is asserted (for two clock cycles) only when the EPIC is ...
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ENTITY SERINT IS PORT( s_clk s_frame_B : IN int_B s_int ); END SERINT; -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ARCHITECTURE BEHAVIOR OF SERINT IS -- Architecture Declarations SIGNAL q : std_logic_vector(3 downto 0); CONSTANT one : std_logic_vector(3 downto 0) ...
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ELSIF (q = '1000') THEN ELSIF (q = '1001') THEN ELSIF (q = '1010') THEN ELSIF (q = '1011') THEN ELSIF (q = '1100') THEN ELSIF (q = '1101') THEN ELSIF (q = '1110') THEN ELSE END IF; END PROCESS ...
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Figure 20. The sequence of interrupt handling is as follows: 1. MPC107 received interrupt (from PCI or internal sources) 2. MPC107 forwards interrupt to CPU “A” 3. CPU “A” handles interrupt, clears interrupt at the source 4. If interrupt is ...
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If I/O devices are smaller than the SDRAM/ROM bus width, software alignment must be used • Only RCS0 and RCS1 support a special byte-wide access mode • All memory and I/O devices have the same (programmable) timing Using the ...
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MDH(8:15) MDH(16:23) MDH(0:7) ADDRESS UART 7C00_0000 REG #0 UART 7C00_0008 REG #1 UART 7C00_0010 REG #2 UART 7C00_0018 REG #3 ... UART Assuming that the UART is a typical PC16550-compatible device, it has 8 sequentially-addressable registers. When this ...
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Adjusting I/O Timings The MPC107 controls the timing for access to ROM and I/O devices using the MCCR1.ROMFAL bits, which sets the number of bus clock cycles needed to perform read and write cycles to devices. Since there is ...
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As seen in , the WE signal extends beyond the CS assertion interval. For devices which require particular relationships between CS and WE, AS can be used with simple logic to adjust the relationships for such I/O or Flash/ROM devices. ...
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To simplify system design, the MPC107 also has the capability of asserting a reset signal (HRESET_CPU) to the PowerPC processor, as shown this configuration, the MPC107 asserts the processor HRESET pin when the PCIRST# signal is asserted. ...
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Reset +3.3V Monitor +2.5V RST Figure 27. MPC107 Self-Hard-Reset Connections As shown in Figure 27, the SRESET output in the EPIC unit is used to drive system reset logic, assuring that all other devices see a general reset signal. Note ...
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A1 NOTE: This is an x-ray view through the MPC107. LEGEND - CBGA Pad - VIA Figure 28. MPC107 Escape Pattern With Components Note: In Figure 28, the MPC107 pad pattern is divided into four quadrants. Each BGA pad (typically ...
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... World Wide Web Addresses: http://www.motorola.com/PowerPC http://www.motorola.com/NetComm http://www.motorola.com/ColdFire Table 13. Reference Documentation Author Howard Johnson and Martin Graham T. C. Edwards Gary Milliorn Gary Milliorn are registered trademarks of Motorola, Inc. Motorola, Inc Equal Document Prentice-Hall ISBN 0-133-95724-1 John Wiley, NY, 1981 AN1722/D AN1846/D AN1849/D ...