AN1849 Motorola / Freescale Semiconductor, AN1849 Datasheet - Page 28

• Manufacturer Part Number: AN1849
• Description: MPC107 Design Guide
• Manufacturer: Motorola / Freescale Semiconductor

The sequence of interrupt handling is as follows:
Note that this method requires more effort on the part of CPU “A” than on CPU “B”. CPU “A” must actually
perform part of the typical interrupt handling process, sufficient to clear the interrupt source. If it did not do
this, the interrupt would likely immediately cause another interrupt exception. So CPU “A” must perform
at least part of every interrupt exception. CPU “B” is relegated to handling the data processing side.
The fourth method is a variation of this one, but requires even more careful attention to software design. If
the INT signal from the MPC107 is connected to both processors, both processors must handle every
interrupt. To do this, the software must determine (based upon its CPU number, via the EPIC unit) whether
to handle the interrupt or to ignore it while the other CPU. The determination of CPU number and division
of labor need be done only during startup. The limitation of this method is that a CPU will suffer needless
interrupts and will be idled until the other processor handles the exception (and re-enables interrupt
handling).
Whichever of these methods are chosen depends upon the system requirements. For maximum performance
and flexibility, or for true SMP architectures, an external OpenPIC interrupt controller will be required. If
some software overhead can be tolerated, a glueless non-symmetric MP system can be designed with one
of the above approaches.
1.9 I/O Interfacing
The MPC107 has four ROM chip selects, RCS(0:3), which may be used to attach ROM, flash memory or
general-purpose I/O to the memory interface. RCS0 is reserved for initialization code fetched after
HRESET is deasserted, but the others may be used for other code or for memory-mapped I/O devices. There
are some limitations of the memory controller that govern how the RCS pins may be used:
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1. MPC107 received interrupt (from PCI or internal sources)
2. MPC107 forwards interrupt to CPU “A”
3. CPU “A” handles interrupt, clears interrupt at the source
4. If interrupt is for CPU “A”, continue in interrupt handler.
5. If interrupt is for CPU “B”, sets INTA output in I
6. Return from exception
•
No I/O device can be wider than the SDRAM/ROM bus width
Figure 20.
INT(0:4)
MPC107
MPC107 Multiprocessing Reset Logic
MPC7400
MPC107 Design Guide
“A”
INT
INT
INTA
2
O message unit
MPC7400
INT
“B”