AN1849 Motorola / Freescale Semiconductor, AN1849 Datasheet - Page 15

• Manufacturer Part Number: AN1849
• Description: MPC107 Design Guide
• Manufacturer: Motorola / Freescale Semiconductor

1.5.4 ROM
The MPC107 supports up to four ROM devices for code and data storage. Most embedded systems will need
at least one ROM to boot from, and the remaining chip selects may be used as needed, including for general
I/O purposes (see Section 1.9, “I/O Interfacing” on page 28). While the ROM controller has some options
on the width of the ROMs used, it is not infinitely flexible. In particular, other than the 8-bit ROM modes,
which are handled in a special manner, the width of a ROM is always the same as the width of the SDRAM.
Table 7 shows the only allowable combinations.
No other combinations are possible; in particular, it is not possible to use 64-bit SDRAMs and 32-bit ROMs.
The ROM controller shares the memory address lines, bank selects, write enable, and the memory data
parity lines to create the ROM control signals (AR, FOE, WE) and adds the dedicated ROM control signals
(RCS(0:3) and FOE. Table 8 shows this remapping.
The ROM addresses are renamed “AR” instead of “A” because the latter is the standard name already used
for the PowerPC processor address bus. Note that since the ROM controller shares the address lines used by
the SDRAM controller, large ROM arrays can increase the capacitive loading and slow down the overall
Notes:
1 If the SDRAM is 32-bits wide, the processor is 32-bits wide as well. The
DBUS(0:2) Setting
MPC750 does not support 32-bit wide mode (the 60X does), so this mode
should not be used with an MPC750.
SDMA0
SDMA(1:10)
SDBA0
PAR7
PAR(6:0)
SDBA1
SDMA(11:13)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
MPC107 Signal
Table 8. MPC107 ROM Address Renames
Table 7. Allowable MPC107 ROM Sizes
ROM0
32
32
64
64
8
8
8
8
MPC107 Design Guide
ROM Address Signal
ROM1
32
32
64
64
8
8
8
8
AR(13:19)
AR(21:23)
AR(1:10)
AR11
AR12
AR20
AR0
ROM2
32
32
32
32
64
64
64
64
ROM3
32
32
32
32
64
64
64
64
Typical ROM
Destination
A(13:19)
A(21:23)
Using 32-bit SDRAM
Using 64-bit SDRAM
A(1:10)
A11
A12
A20
A0
width1
Notes
width
Memory Architecture
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