AN1849 Motorola / Freescale Semiconductor, AN1849 Datasheet - Page 11

• Manufacturer Part Number: AN1849
• Description: MPC107 Design Guide
• Manufacturer: Motorola / Freescale Semiconductor

Figure 7 shows how adding to the CPU_CLK traces (of delay t
to communicate with PowerPC processors.
1.5 Memory Architecture
The MPC107 contains a high-speed SDRAM/DRAM memory controller and a ROM controller. The
memory interface is completely separate from the processor bus, so that heavy loading on the SDRAM bus
will not affect the processor bus. In addition, the memory interface of the MPC107, unlike the MPC106, has
internal registered buffers which allow it to increase performance and to implement “on-the-fly” ECC. Since
EDO is more-or-less a subset of SDRAM, it will not be covered further.
1.5.1 Banks
A momentary digression on the use of the term “bank.” The meaning of “bank” varies depending upon what
level of a memory system you are looking at. Within the SDRAM memory silicon, the term is used to
describe devices which can maintain 2-to-4 open pages simultaneously (no activation delay). This is the
meaning of bank as used to set the MCCR1 register in the MPC107: 64 Mbit/4-banks, 64 Mbit/2-banks, etc.
The MPC107 uses this information to drive the bank address pins (BA(0:1)) properly. The term “internal
bank” is also often used.
At the level of a memory module (SODIMM, DIMM, etc.), the term bank is used to describe the number of
independently selectable groups of SDRAM components. A standard SDRAM module contains 64-bits of
memory using components of various widths (4, 8 or 16 bits). Each bank of memory is controlled by a pair
of chip select pins (CS0 and CS2 for 64-bit modules), which are connected together to configure the module
as a 64-bit bus. To increase density, some modules have a second, independent set of components controlled
by a second pair of chip selects (CS1 and CS3). This is described in the I
“bank”, and such devices are referred to as “dual-bank” modules, as opposed to “single-bank” modules.
Lastly, the MPC107 refers to a bank as one of eight possible groups of memory, each of which is controlled
by a separate chip select pin (CS(0:7)). MPC107 banks have different sizes and types and can be positioned
at various addresses, but have common timing.
Note that a dual-bank DIMM is typically wired up to two MPC107 banks, as shown in section on page 12.
When DIMMs are connected in this fashion, what happens when single-bank DIMMs are inserted? The
result is that the MPC107 bank controlling CS1 is unused; to get a contiguous range of memory, the starting
and ending addresses of banks 2-7 should be adjusted to skip over unused physical banks.
SDRAM_SYNC_OUT
SDRAM_SYNC_IN
sys_logic_clk
CPU_CLK0
at MPC107
CPU_CLK0
at CPU
0 ns
t
EXTRA=1.0
t
LOOP=1.0
Figure 7. Resynchronizing CPU Clocks
5 ns
MPC107 Design Guide
10 ns
EXTRA
) restores the synchronization needed
2
C SPD EEPROM as a second
Memory Architecture
11