AN1849 Motorola / Freescale Semiconductor, AN1849 Datasheet - Page 12

• Manufacturer Part Number: AN1849
• Description: MPC107 Design Guide
• Manufacturer: Motorola / Freescale Semiconductor

1.5.2 Memory Connections
Connecting memory to the MPC107 is fairly straightforward, with the exception of the SDRAM clock
signals, which have been discussed in section 1.4.3 on page 5. Otherwise, most signals on the MPC107 have
the same name as the signals on the memory devices/modules, and can be connected one-to-one. shows a
typical MPC107 memory connection. The remaining signals such as SDA, SCK, SA(0:2), etc. are either
standard I
There are three particular considerations to keep in mind when connecting the memory system:
The association between DQM and MDH/MDL is important when the MPC107 is in non-ECC/non-parity
memory modes, since it requires the ability to modify a single byte. In ECC or parity modes, all DQMs are
driven to the same value since only 64-bit quantities are read or written, so in that one case the DQMs can
be freely associated.
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•
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Each physical bank of memory must connect to one and only one
Memory data connects to the memory data bus (MDH/MDL/PAR), not the processor data
bus (DH/DL/DP)
The DQM signals must match with the corresponding byte lane:
2
C controls for module information or are unused.
MPC107
SDMA(13:0)
MDH(0:31)
SDBA(1:0)
MDL(0:31)
DQM(0:7)
PAR(0:7)
DQM0
DQM1
DQM2
DQM3
DQM4
DQM5
DQM6
DQM7
SDRAS
SDCAS
CS(0:1)
CS(2:3)
CS(4:5)
CS(6:7)
CKE
WE
⇔
⇔
⇔
⇔
⇔
⇔
⇔
⇔
Figure 8. MPC107 Memory Connections
ΜDH(0:7)
ΜDH(8:15)
ΜDH(16:23)
ΜDH(24:31)
ΜDL(0:7)
ΜDL(8:15)
ΜDL(16:23)
ΜDL(24:31)
MPC107 Design Guide
DIMM
#1
DIMM
#2
CS
line