AN1849 Motorola / Freescale Semiconductor, AN1849 Datasheet - Page 10

• Manufacturer Part Number: AN1849
• Description: MPC107 Design Guide
• Manufacturer: Motorola / Freescale Semiconductor

Typical zero-delay buffers generate output clocks that are aligned to within 350ps of the input clock, which
of course is not really zero, but can be adjusted to effectively zero by lengthening the MPC107 DLL
feedback path. This effectively treats the delay through the zero-delay buffer as extra trace length, so the
feedback path is lengthened using the formula:
where 58 ps/cm (147 ps/in) is the propagation time of our example PCB trace (refer to Table 2 for
assumptions).
Note that similar zero-delay buffers are included on registered SDRAM DIMMs. If a system restricts the
type of memory usable to registered DIMMs, it may be possible to eliminate the extra zero-delay buffers.
1.4.6 CPU Clocks
The MPC107 also supplies three clocks which can be used to clock two processors and one local-bus slave
device, as needed. An unfortunate side-effect of the MPC107 clock generator architecture is that the CPU
clocks are actually generated by the SDRAM clock DLL, so CPU clocks are always synchronous to the
SDRAM clocks. When the DLL feedback is used to adjust the timing relationship between the
SDRAM_CLK and the SDRAM, the processor bus will be inadvertently affected.
The solution to this is to add the same amount of delay to the CPU clock that is added to the SDRAM_SYNC
feedback path. Since 1 ns of feedback trace length causes the SDRAM_CLK signals to begin 1 ns early
(relative to the internal bus clock), adding 1 ns of trace length to the CPU_CLK signals will re-synchronize
the CPU clocks so that they arrive at the destination in sync with the internal MPC107 bus clock.
10
PCISYNC_IN
OSC_IN
MPC107
Figure 6. Clock Expansion Using Zero-Delay Buffers
ExtraMPC107delay
x
x
x
x
x
x
x
MPC107 Design Guide
CPUCLK0
SDRAM_CLK0
SDRAM_CLK2
feedback
unused
=
------------------- -
58ps/cm
350ps
SDRAM
SDRAM
SDRAM
SDRAM
MPC7400