AN1849 Motorola / Freescale Semiconductor, AN1849 Datasheet - Page 5

• Manufacturer Part Number: AN1849
• Description: MPC107 Design Guide
• Manufacturer: Motorola / Freescale Semiconductor

This architecture uses a 33 MHz oscillator (or frequency synthesizer) to create the baseline PCI clock. The
clock is distributed equally to the MPC107 core logic via PCI_SYNC_IN as well as the PCICLK pins of the
other PCI devices.
1.4.2 Agent Mode Clocking
When configured as an agent, the MPC107 will typically be part of a larger system, whether as a component
on an embedded board, or as a PCI card plugged into a motherboard. As such, it is usually not expected to
provide skew-controlled clocks to all other PCI devices on the PCI bus, but instead receives a clock from
another source. For this environment, the PCI clock tree is not usually used. Figure 3 shows an example of
a typical agent-mode MPC107 system.
Agents usually receive a clock signal (PCICLK) generated elsewhere in the system which drives the
PCISYNC_IN pin. Because there is a small amount of delay from OSC_IN to PCICLK(0:4), it is not
normally recommended that PCICLK flow through the PCI clock buffer, as this would increase the overall
system skew. If absolutely required, it may be possible to do so by correspondingly shortening the PCICLK
trace. On an embedded motherboard there is usually more flexibility about clock trace lengths as opposed
to a PC-type plug-in PCI card.
1.4.3 Memory Clocks
The MPC107 provides four clocks signals, SDRAM_CLK(0:3), which can be used to drive one or more
SDRAM components. The MPC107 controls these clocks with a digital locked loop (DLL) which can be
used to adjust the relationship between clocks and SDRAM control signals or data. Such deliberate skewing
of clocks is often required to compensate for a heavily loaded memory bus, or to communicate with
SDRAM components which do not exactly match the AC timing provided by the MPC107. The usual
method of creating skew is to add PCB trace length to clocks This is especially true in the case of PC100
SDRAM components or modules, which require additional output hold time.
PCICLK
system
rest of
PCI DEVICE
PCI DEVICE
usually
6.0 cm
unused
Figure 3. Agent Clock Architecture
MPC107 Design Guide
PCISYNC_IN
OSC_IN
MPC107
SDRAM_CLK3
SDRAM_CLK0
x
CPUCLK0
x
x
x
x
unused
feedback
MPC7400
SDRAM
Clocks
5