AN1849 Motorola / Freescale Semiconductor, AN1849 Datasheet - Page 3

• Manufacturer Part Number: AN1849
• Description: MPC107 Design Guide
• Manufacturer: Motorola / Freescale Semiconductor

In general, designers who are familiar with the MPC106 will find that the MPC107 increases performance,
eases design effort, and decreases overall board space. Designers new to the PowerPC family will find that
the MPC107 supplies almost all of the interface circuitry needed for the PowerPC processors, with the
remainder being the familiar sort of signals all embedded systems need (power, reset, etc.).
1.2 Processor Interface
The MPC107 provides all the interface signals needed to interface between the PowerPC processor and
other devices (such as SDRAM, ROM, PCI, etc.). In general, there will be a one-to-one connection between
the MPC107 and the CPU; at most there would be three loads (the MPC107, two CPUs and a local-bus-slave
device). Table 1 lists all needed connections between the MPC107 and processor bus devices.
1
2
There are other signals such as MCP, INT, and HRESET which are provided by the MPC107 and connected
to the PowerPC CPU; however these signals are not part of the 60X bus protocol so refer to Section 1.8,
“Interrupt Controller” on page 23 and Section 1.10, “Reset” on page 32, respectively, for information on
special pins.
1.3 Local Bus Slave
The local bus slave (LBS) is a means by which a user-created I/O device can accept 60X bus cycles with
minimal intervention by the MPC107 (which otherwise handles all 60X bus transactions). Designers who
need a high-speed I/O channel or special types of memories (FIFOs, dual-port SRAMs, etc.) may use the
LBS to control such devices.
Designing an LBS interface is covered in more detail in the application note, “Designing a Local Bus Slave
I/O Controller,” and so will not be covered in detail here. In terms of system design, however, the LBS
Pull-ups on the address bus are optional and only needed where power consumption is a concern during
Not implemented on the MPC7400 or other G3 processors.
instances where the PowerPC CPU and MPC107 are in a low-power idle state (where the address bus is rarely
driven). If these circumstances do not apply, the address bus pull-ups are not needed.
DH(0:31), DL(0:31),
BR0, BG0, DBG0
BR1, BG1, DBG1
TSIZ(0:2), TBST
AACK, ARTRY
MPC107 Pin
CI, GBL, WT,
TS, TA, TEA
DP(0:7)
A(0:31)
TT(0:4)
none
Table 1. MPC107 Processor Bus Connections
PowerPC CPU
BR, BG, DBG
BR, BG, DBG
ABB, DBB
same
same
same
same
same
same
same
Pin
2
MPC107 Design Guide
Required?
External
Pull-up
No
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
1
Address bus
Data Bus (note: not the same as the
MDH/MDL/PAR memory bus).
Address info (size, burst)
Address types (read, write, atomic, cache)
Address coherency
Address/Data tenure start and completion
Address tenure completion signals
Bus request/grant
Bus request/grant (optional second CPU)
Bus busy (unused by MPC107)
Description
Processor Interface
3