AN1849 Motorola / Freescale Semiconductor, AN1849 Datasheet - Page 29

• Manufacturer Part Number: AN1849
• Description: MPC107 Design Guide
• Manufacturer: Motorola / Freescale Semiconductor

Using the RCS signals to control I/O is fairly straightforward as long as the devices can fit within these
limitations. If the devices requires individual timing, or asynchronous timing controls, the local-bus slave
interface is more suitable and flexible.
Figure 21 shows an example system with both flash memory and I/O connected to the memory controller
of the MPC107. As long as the device has a typical memory-type interface (chip-select, output-enable and
write-enable) it should be possible to connect it to an MPC107.
When I/O devices are smaller than the programmed bus width, as with an 8-bit UART on the 32- or 64-bit
RCS2 space, software must align reads and writes to account for the byte lanes which are not used. Since
the MPC107 expects the device to be 64-bits, it does not adjust the addresses and does not provide byte lane
write controls (as would the SDRAM interface), so software must compensate by adjusting addresses used.
Figure 22 shows an example of byte lane usage.
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MPC107
If I/O devices are smaller than the SDRAM/ROM bus width, software alignment must be used
Only RCS0 and RCS1 support a special byte-wide access mode
All memory and I/O devices have the same (programmable) timing
MDH(0:31)
MDL(0:31)
AR(23:0)
RCS2
RCS0
RCS1
FOE
WE
Figure 21. Using RCS pins for I/O
MPC107 Design Guide
WE
CS
WE
CS
CS
A(19:0)
OE
A(3:0)
A(1:0)
OE
OE
WE
(optional)
(optional)
BUFFER
FLASH
UART
D(0:15)
FIFO
D(0:7)
D(0:7)
MDH(0:7)
MDL(0:15)
MDH(0:7)
I/O Interfacing
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