AN1849 Motorola / Freescale Semiconductor, AN1849 Datasheet - Page 31

• Manufacturer Part Number: AN1849
• Description: MPC107 Design Guide
• Manufacturer: Motorola / Freescale Semiconductor

1.9.1 Adjusting I/O Timings
The MPC107 controls the timing for access to ROM and I/O devices using the MCCR1.ROMFAL bits,
which sets the number of bus clock cycles needed to perform read and write cycles to devices. Since there
is only one register setting, all devices on the ROM controller must share the exact same timing for all
accesses. If a slow flash is used, say 150 ns, then any I/O devices will also share a 150 ns access time.
Since the MCCR1.ROMFAL settings may be changed at any time, there are three methods to compensate
for this problem:
The first two solutions are simplest, and basically involve cases where a system can avoid accessing code or
data in the ROM after system initialization has completed. In these cases, there is no need to retain a slow
MCCR1.ROMFAL setting since the slow ROM/Flash devices are no longer accessed. In such cases, the
software can simply change MCCR1.ROMFAL shortly after the last access to the ROM has completed. An
example of this type of system is the Motorola DINK32 debugger, which copies itself to RAM and no longer
uses the ROM thereafter.
The last solution is fairly complex, requiring tightly-controlled software assistance; this approach would be
required in situations where, due to size or cost limitations, software must run partially or entirely from
Flash/ROM. Since changes to the MCCR1.ROMFAL setting can affect the ability to read instructions from
the ROM, the software must ensure that code is resident in cache. Once cache-bound, the software can
increase the speed of I/O accesses, perform the access (or multiple accesses), and then restore the slower
MCCR1.ROMFAL settings. In essence, the software changes the MCCR1.ROMFAL settings every time it
accesses the I/O device. Due to the complexity of this method, it is typically only used for critical I/O, but
it is particularly well-suited to interrupt drivers, where access to I/O is encapsulated.
1.9.2 PortX
Despite the name, the PortX facility is not a separate, general-purpose I/O subsystem, it is intimately tied to
the ROM memory controller. PortX is best thought of as a programmable address strobe signal (AS) which
can be asserted in the middle of all ROM I/O cycles. This is only enhancement to I/O interfacing which
PortX brings; however, it is quite useful to strobe addresses into a multiplexed address/data device, and also
to alter the I/O signals for devices which have particular restrictions on the relationships between RCSx,
FOE, and WE. Figure 23 shows an example of the AS signal in a PortX access cycle.
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Copy program code to SDRAM and run from SDRAM; permanently speed up MCCR1.ROMFAL
Run or copy program code from PCI; permanently speed up MCCR1.ROMFAL
Dynamically change MCCR1.ROMFAL
A19-A0
RCSx
FOE
DATA
CLK
WE
AS
Figure 23. PortX Access Timing
ASFALL
MPC107 Design Guide
ASRISE
I/O Interfacing
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