SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 508

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

26.18.20 SMC Timings Register
Name:
Address:
Access:
Reset:
• TCLR: CLE to REN Low Delay
Command Latch Enable falling edge to Read Enable falling edge timing.
Latch Enable Falling to Read Enable Falling = (TCLR[3] * 64) + TCLR[2:0] clock cycles.
• TADL: ALE to Data Start
Last address latch cycle to the first rising edge of WEN for data input.
Last address latch to first rising edge of WEN = (TADL[3] * 64) + TADL[2:0] clock cycles.
• TAR: ALE to REN Low Delay
Address Latch Enable falling edge to Read Enable falling edge timing.
Address Latch Enable to Read Enable = (TAR[3] * 64) + TAR[2:0] clock cycles.
• OCMS: Off Chip Memory Scrambling Enable
When set to one, the memory scrambling is activated.
• TRR: Ready to REN Low Delay
Ready/Busy signal to Read Enable falling edge timing.
Read to REN = (TRR[3] * 64) + TRR[2:0] clock cycles.
• TWB: WEN High to REN to Busy
Write Enable rising edge to Ready/Busy falling edge timing.
Write Enable to Read/Busy = (TWB[3] * 64) + TWB[2:0] clock cycles.
• RBNSEL: Ready/Busy Line Selection
This field indicates the selected Ready/Busy Line from the RBN bundle.
508
508
NFSEL
31
23
15
–
–
7
SAM3X/A
SAM3X/A
0x400E007C [0], 0x400E0090 [1], 0x400E00A4 [2], 0x400E00B8 [3], 0x400E00CC [4], 0x400E00E0 [5],
0x400E00F4 [6], 0x400E0108 [7]
SMC_TIMINGSx [x=0..7]
Read-write
0x00000000
30
22
14
–
–
6
TADL
RBNSEL
29
21
13
–
–
5
OCMS
28
20
12
–
4
27
19
11
3
26
18
10
2
TCLR
TWB
TRR
TAR
25
17
9
1
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
24
16
8
0