SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 161
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SAM3X8E
Manufacturer Part Number
SAM3X8E
Description
Manufacturer
Atmel Corporation
- Current page: 161 of 1465
- Download datasheet (26Mb)
11.20.7.4
11.20.7.5
11.20.7.6
• Priority, byte offset 3
• Priority, byte offset 2
• Priority, byte offset 1
• Priority, byte offset 0
Each priority field holds a priority value, 0-15. The lower the value, the greater the priority of the corresponding interrupt.
The processor implements only bits[7:4] of each field, bits[3:0] read as zero and ignore writes.
See
interrupt priority array, that provides the software view of the interrupt priorities.
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
“The CMSIS mapping of the Cortex-M3 NVIC registers” on page 153
31
23
15
31
23
15
31
23
15
7
7
7
IPR2
IPR1
IPR0
30
22
14
30
22
14
30
22
14
6
6
6
29
21
13
29
21
13
29
21
13
5
5
5
28
20
12
28
20
12
28
20
12
4
4
4
IP[11]
IP[10]
IP[9]
IP[8]
IP[7]
IP[6]
IP[5]
IP[4]
IP[3]
IP[2]
IP[1]
IP[0]
27
19
11
27
19
11
27
19
11
3
3
3
for more information about the IP[0] to IP[29]
26
18
10
26
18
10
26
18
10
2
2
2
25
17
25
17
25
17
9
1
9
1
9
1
SAM3X/A
SAM3X/A
24
16
24
16
24
16
8
0
8
0
8
0
161
161
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