SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 1100

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

UOTGHS_HSTPIPIMRx.FIFOCON
Figure 39-27. Example of an OUT Pipe with two Data Banks and no Bank Switching Delay
Figure 39-28. Example of an OUT Pipe with two Data Banks and a Bank Switching Delay
39.5.3.12
39.5.3.13
1100
1100
UOTGHS_HSTPIPISRx.TXOUTI
UOTGHS_HSTPIPIMRx.FIFOCON
Global interrupts
UOTGHS_HSTPIPISRx.TXOUTI
SAM3X/A
SAM3X/A
CRC Error
Interrupts
T h i s e r r o r e x i s t s o n l y fo r i s o ch r o n o u s I N p i p e s . It s e t s t h e C R C E r r o r I n te r r u p t
(UOTGHS_HSTPIPISRx.CRCERRI) bit, which triggers a PEP_x interrupt if then the CRC Error
Interrupt Enable (UOTGHS_HSTPIPIMRx.CRCERRE) bit is one.
A CRC error can occur during IN stage if the UOTGHS detects a corrupted received packet. The
IN packet is stored in the bank as if no CRC error had occurred (UOTGHS_HSTPIPISRx.RXINI
is set).
See the structure of the USB host interrupt system on
There are two kinds of host interrupts: processing, i.e. their generation is part of the normal pro-
cessing, and exception, i.e. errors (not related to CPU exceptions).
The processing host global interrupts are:
• The Device Connection Interrupt (UOTGHS_HSTISR.DCONNI)
• The Device Disconnection Interrupt (UOTGHS_HSTISR.DDISCI)
• The USB Reset Sent Interrupt (UOTGHS_HSTISR.RSTI)
• The Downstream Resume Sent Interrupt (UOTGHS_HSTISR.RSMEDI)
• The Upstream Resume Received Interrupt (UOTGHS_HSTISR.RXRSMI)
SW
SW
write data to CPU
write data to CPU
BANK 0
BANK 0
SW
SW
OUT
OUT
SW
SW
write data to CPU
(bank 0)
DATA
write data to CPU
BANK 1
(bank 0)
DATA
BANK 1
ACK
HW
SW
Figure 39-6 on page
ACK
HW
SW
OUT
SW
OUT
write data to CPU
SW
(bank 1)
DATA
write data to CPU
BANK0
BANK0
1074.
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
(bank 1)
DATA
ACK
ACK