SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 199
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SAM3X8E
Manufacturer Part Number
SAM3X8E
Description
Manufacturer
Atmel Corporation
- Current page: 199 of 1465
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Any access by unprivileged software that does not address an enabled memory region causes a memory management
fault.
XN and Strongly-ordered rules always apply to the System Control Space regardless of the value of the ENABLE bit.
When the ENABLE bit is set to 1, at least one region of the memory map must be enabled for the system to function unless
the PRIVDEFENA bit is set to 1. If the PRIVDEFENA bit is set to 1 and no regions are enabled, then only privileged soft-
ware can operate.
When the ENABLE bit is set to 0, the system uses the default memory map. This has the same memory attributes as if the
MPU is not implemented, see
and unprivileged software.
When the MPU is enabled, accesses to the System Control Space and vector table are always permitted. Other areas are
accessible based on regions and whether PRIVDEFENA is set to 1.
Unless HFNMIENA is set to 1, the MPU is not enabled when the processor is executing the handler for an exception with
priority –1 or –2. These priorities are only possible when handling a hard fault or NMI exception, or when FAULTMASK is
enabled. Setting the HFNMIENA bit to 1 enables the MPU when operating with these two priorities.
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Table 11-34 on page
195. The default memory map applies to accesses from both privileged
SAM3X/A
SAM3X/A
199
199
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