SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 459

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

26.14.4
Figure 26-27. NWAIT Latency
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
intenally synchronized
NWAIT signal
NBS0, NBS1,
NWAIT Latency and Read/Write Timings
NWAIT
A [23:2]
A0,A1
MCK
NRD
There may be a latency between the assertion of the read/write controlling signal and the asser-
tion of the NWAIT signal by the device. The programmed pulse length of the read/write
controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1
cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT
signal assertion. This is true in frozen mode as well as in ready mode. This is illustrated on
ure
When EXNW_MODE is enabled (ready or frozen), the user must program a pulse length of the
read and write controlling signal of at least:
minimal pulse length = NWAIT latency + 2 resynchronization cycles + 1 cycle
26-27.
4
NWAIT latency
3
2 cycle resynchronization
minimal pulse length
2
EXNW_MODE = 10 or 11
READ_MODE = 1 (NRD_controlled)
NRD_PULSE = 5
Read cycle
1
0
0
WAIT STATE
0
SAM3X/A
SAM3X/A
Fig-
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