SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 1119
SAM3X8E
Manufacturer Part Number
SAM3X8E
Description
Manufacturer
Atmel Corporation
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39.6.2.2
Name:
Address:
Access:
• DMA_x: DMA Channel x Interrupt
This bit is set when an interrupt is triggered by the DMA channel x. This triggers a USB interrupt if DMA_x is one.
This bit is cleared when the UOTGHS_DEVDMASTATUSx interrupt source is cleared.
• PEP_x: Endpoint x Interrupt
This bit is set when an interrupt is triggered by the endpoint x (UOTGHS_DEVEPTISRx, UOTGHS_DEVEPTIMRx). This
triggers a USB interrupt if UOTGHS_DEVIMR.PEP_x is one.
This bit is cleared when the interrupt source is serviced.
• UPRSM: Upstream Resume Interrupt
This bit is set when the UOTGHS sends a resume signal called “Upstream Resume”. This triggers a USB interrupt if
UOTGHS_DEVIMR.UPRSME is one.
This bit is cleared when the UOTGHS_DEVICR.UPRSMC bit is written to one to acknowledge the interrupt (USB clock
inputs must be enabled before).
• EORSM: End of Resume Interrupt
This bit is set when the UOTGHS detects a valid “End of Resume” signal initiated by the host. This triggers a USB interrupt
if UOTGHS_DEVIMR.EORSME is one.
This bit is cleared when the UOTGHS_DEVICR.EORSMC bit is written to one to acknowledge the interrupt.
• WAKEUP: Wake-Up Interrupt
This bit is set when the UOTGHS is reactivated by a filtered non-idle signal from the lines (not by an upstream resume).
This triggers an interrupt if UOTGHS_DEVIMR.WAKEUPE is one.
This bit is cleared when the UOTGHS_DEVICR.WAKEUPC bit is written to one to acknowledge the interrupt (USB clock
inputs must be enabled before).
This bit is cleared when the Suspend (SUSP) interrupt bit is set.
This interrupt is generated even if the clock is frozen by the UOTGHS_CTRL.FRZCLK bit.
• EORST: End of Reset Interrupt
This bit is set when a USB “End of Reset” has been detected. This triggers a USB interrupt if UOTGHS_DEVIMR.EORSTE
is one.
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
PEP_3
31
23
15
–
–
7
–
Device Global Interrupt Status Register
UOTGHS_DEVISR
0x400AC004
Read-only
UPRSM
DMA_6
PEP_2
30
22
14
–
6
EORSM
DMA_5
PEP_9
PEP_1
29
21
13
5
WAKEUP
DMA_4
PEP_8
PEP_0
28
20
12
4
DMA_3
EORST
PEP_7
27
19
11
–
3
DMA_2
PEP_6
SOF
26
18
10
–
2
DMA_1
PEP_5
MSOF
25
17
9
–
1
SAM3X/A
SAM3X/A
PEP_4
SUSP
24
16
–
8
–
0
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