SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 1013

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

38.6.5.6
38.6.5.7
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Interrupts
Write Protect Registers
Depending on the interrupt mask in the PWM_IMR1 and PWM_IMR2 registers, an interrupt can
be generated at the end of the corresponding channel period (CHIDx in the PWM_ISR1 regis-
ter), after a fault event (FCHIDx in the PWM_ISR1 register), after a comparison match (CMPMx
in the PWM_ISR2 register), after a comparison update (CMPUx in the PWM_ISR2 register) or
according to the transfer mode of the synchronous channels (WRDY, ENDTX, TXBUFE and
UNRE in the PWM_ISR2 register).
If the interrupt is generated by the flags CHIDx or FCHIDx, the interrupt remains active until a
read operation in the PWM_ISR1 register occurs.
If the interrupt is generated by the flags WRDY or UNRE or CMPMx or CMPUx, the interrupt
remains active until a read operation in the PWM_ISR2 register occurs.
A channel interrupt is enabled by setting the corresponding bit in the PWM_IER1 and
PWM_IER2 registers. A channel interrupt is disabled by setting the corresponding bit in the
PWM_IDR1 and PWM_IDR2 registers.
To prevent any single software error that may corrupt PWM behavior, the registers listed below
can be write-protected by writing the field WPCMD in the
on page 1049
• Register group 0:
• Register group 1:
• Register group 2:
• Register group 3:
• Register group 4:
• Register group 5:
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“PWM Clock Register” on page 1018
“PWM Disable Register” on page 1020
“PWM Sync Channels Mode Register” on page 1026
“PWM Channel Mode Register” on page 1056
“PWM Stepper Motor Mode Register” on page 1048
“PWM Channel Period Register” on page 1060
“PWM Channel Period Update Register” on page 1061
“PWM Channel Dead Time Register” on page 1064
“PWM Channel Dead Time Update Register” on page 1065
“PWM Fault Mode Register” on page 1041
“PWM Fault Protection Value Register” on page 1044
“PWM Fault Protection Enable Register 1” on page 1045
“PWM Fault Protection Enable Register 2” on page 1046
(PWM_WPCR). They are divided into 6 groups:
“PWM Write Protect Control Register”
SAM3X/A
SAM3X/A
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