SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 987

• Manufacturer Part Number: SAM3SD8C
• Manufacturer: Atmel Corporation

When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to
microcontroller memory. The number of bytes received is available in RXBYTECNT field. Bank 1 FIFO values are read
through UDP_FDRx register. Once a transfer is done, the device firmware must release Bank 1 to the USB device by clear-
ing RX_DATA_BK1.
After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before
accessing DPR.
• DIR: Transfer Direction (only available for control endpoints)
Read-write
0 = Allows Data OUT transactions in the control data stage.
1 = Enables Data IN transactions in the control data stage.
Refer to Chapter 8.5.3 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the control data stage.
This bit must be set before UDP_CSRx/RXSETUP is cleared at the end of the setup stage. According to the request sent in
the setup data packet, the data stage is either a device to host (DIR = 1) or host to device (DIR = 0) data transfer. It is not
necessary to check this bit to reverse direction for the status stage.
• EPTYPE[2:0]: Endpoint Type
Read-Write
• DTGLE: Data Toggle
Read-only
0 = Identifies DATA0 packet.
1 = Identifies DATA1 packet.
Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet
definitions.
• EPEDS: Endpoint Enable Disable
Read:
0 = Endpoint disabled.
1 = Endpoint enabled.
Write:
0 = Disables endpoint.
1 = Enables endpoint.
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
Value
000
001
101
010
110
011
111
Name
CTRL
ISO_OUT
ISO_IN
BULK_OUT
BULK_IN
INT_OUT
INT_IN
Description
Control
Isochronous OUT
Isochronous IN
Bulk OUT
Bulk IN
Interrupt OUT
Interrupt IN
SAM3S8/SD8
SAM3S8/SD8
987
987