SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 402

• Manufacturer Part Number: SAM3SD8C
• Manufacturer: Atmel Corporation

23.12.3
Figure 23-25. NWAIT Assertion in Write Access: Ready Mode (EXNW_MODE = 11)
402
402
internally synchronized
NWAIT signal
SAM3S8/SD8
SAM3S8/SD8
Ready Mode
D[7:0]
NWAIT
A [23:0]
NWE
MCK
NCS
6
In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins
the access by down counting the setup and pulse counters of the read/write controlling signal. In
the last cycle of the pulse phase, the resynchronized NWAIT signal is examined.
If asserted, the SMC suspends the access as shown in
deassertion, the access is completed: the hold step of the access is performed.
This mode must be selected when the external device uses deassertion of the NWAIT signal to
indicate its ability to complete the read or write operation.
If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the
pulse of the controlling read/write signal, it has no impact on the access length as shown in
ure
23-26.
4
5
4
3
3
2
1
2
Write cycle
EXNW_MODE = 11 (Ready mode)
WRITE_MODE = 1 (NWE_controlled)
NWE_PULSE = 5
NCS_WR_PULSE = 7
0
1
0
1
Wait STATE
Figure 23-25
0
1
0
and
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
Figure
23-26. After
Fig-