SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 377
SAM3SD8C
Manufacturer Part Number
SAM3SD8C
Description
Manufacturer
Atmel Corporation
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Figure 23-1.
23.6
23.6.1
Figure 23-2.
23.6.1.1
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
Connection to External Devices
Data Bus Width
SMC
NAND Flash Support
Memory Connections for Four External Devices
Memory Connection for an 8-bit Data Bus
NCS[0] - NCS[3]
A[23:0]
D[7:0]
NWE
NRD
The data bus width is 8 bits.
Figure 23-2
The SMC integrates circuitry that interfaces to NAND Flash devices.
The NAND Flash logic is driven by the Static Memory Controller. It depends on the programming
of the SMC_NFCSx field in the CCFG_SMCNFCS Register on the Bus Matrix User Interface.
For details on this register, refer to the Bus Matrix User Interface section. Access to an external
NAND Flash device via the address space reserved to the chip select programmed.
The user can connect up to 4 NAND Flash devices with separated chip select.
The NAND Flash logic drives the read and write command signals of the SMC on the NANDOE
and NANDWE signals when the NCSx programmed is active. NANDOE and NANDWE are dis-
abled as soon as the transfer address fails to lie in the NCSx programmed address space.
SMC
shows how to connect a 512K x 8-bit memory on NCS2.
A[18:0]
NCS[2]
D[7:0]
NWE
NRD
24
8
NCS0
NCS1
NCS2
Memory Enable
Output Enable
Write Enable
A[23:0]
D[7:0]
NCS3
Write Enable
Output Enable
Memory Enable
D[7:0]
A[18:0]
Memory Enable
Memory Enable
Memory Enable
SAM3S8/SD8
SAM3S8/SD8
377
377
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