SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 404

• Manufacturer Part Number: SAM3SD8C
• Manufacturer: Atmel Corporation

23.12.4
Figure 23-27. NWAIT Latency
404
404
intenally synchronized
NWAIT signal
SAM3S8/SD8
SAM3S8/SD8
NWAIT Latency and Read/Write Timings
NWAIT
A [23:0]
MCK
NRD
There may be a latency between the assertion of the read/write controlling signal and the asser-
tion of the NWAIT signal by the device. The programmed pulse length of the read/write
controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1
cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT
signal assertion. This is true in frozen mode as well as in ready mode. This is illustrated on
ure
When EXNW_MODE is enabled (ready or frozen), the user must program a pulse length of the
read and write controlling signal of at least:
minimal pulse length = NWAIT latency + 2 resynchronization cycles + 1 cycle
23-27.
4
NWAIT latency
3
minimal pulse length
2 cycle resynchronization
2
EXNW_MODE = 10 or 11
READ_MODE = 1 (NRD_controlled)
NRD_PULSE = 5
Read cycle
1
0
0
WAIT STATE
0
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
Fig-