SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 648

• Manufacturer Part Number: SAM3SD8C
• Manufacturer: Atmel Corporation

30.6.3
30.7
30.7.1
30.7.2
Table 30-4.
648
648
SPI Mode
Functional Description
SAM3S8/SD8
SAM3S8/SD8
0
1
2
3
Interrupt
Modes of Operation
Data Transfer
SPI Bus Protocol Mode
CPOL
The SPI interface has an interrupt line connected to the Interrupt Controller. Handling the SPI
interrupt requires programming the interrupt controller before configuring the SPI.
Table 30-3.
The SPI operates in Master Mode or in Slave Mode.
Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register.
The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line
is wired on the receiver input and the MOSI line driven as an output by the transmitter.
If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the
transmitter output, the MOSI line is wired on the receiver input, the SPCK pin is driven by the
transmitter to synchronize the receiver. The NPCS0 pin becomes an input, and is used as a
Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other
purposes.
The data transfers are identically programmable for both modes of operations. The baud rate
generator is activated only in Master Mode.
Four combinations of polarity and phase are available for data transfers. The clock polarity is
programmed with the CPOL bit in the Chip Select Register. The clock phase is programmed with
the NCPHA bit. These two parameters determine the edges of the clock signal on which data is
driven and sampled. Each of the two parameters has two possible states, resulting in four possi-
ble combinations that are incompatible with one another. Thus, a master/slave pair must use the
same parameter pair values to communicate. If multiple slaves are used and fixed in different
configurations, the master must reconfigure itself each time it needs to communicate with a dif-
ferent slave.
Table 30-4
0
0
1
1
Instance
SPI
NCPHA
shows the four modes and corresponding parameter settings.
1
0
1
0
Peripheral IDs
Shift SPCK Edge
21
ID
Falling
Rising
Rising
Falling
Capture SPCK Edge
Rising
Falling
Falling
Rising
SPCK Inactive Level
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
High
High
Low
Low