SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 154

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SAM3SD8C

Manufacturer Part Number
SAM3SD8C
Description
Manufacturer
Atmel Corporation
Datasheets
10.19.3
• CLRENA
Interrupt clear-enable bits.
Write:
0 = no effect
1 = disable interrupt.
Read:
0 = interrupt disabled
1 = interrupt enabled.
154
154
31
23
15
7
SAM3S8/SD8
SAM3S8/SD8
Interrupt Clear-enable Registers
30
22
14
6
The ICER0-ICER1 register disables interrupts, and shows which interrupts are enabled. See:
The bit assignments are:
• the register summary in
Table 10-28 on page 152
29
21
13
5
28
20
12
4
Table 10-27 on page 151
for which interrupts are controlled by each register
CLRENA
CLRENA
CLRENA
CLRENA
27
19
11
3
for the register attributes
26
18
10
2
25
17
9
1
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
24
16
8
0

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