SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 821

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SAM3SD8C

Manufacturer Part Number
SAM3SD8C
Description
Manufacturer
Atmel Corporation
Datasheets
33.7.20
Name:
Address:
Access:
• COVFS: Counter Overflow
0 = the Counter Overflow Interrupt is disabled.
1 = the Counter Overflow Interrupt is enabled.
• LOVRS: Load Overrun
0 = the Load Overrun Interrupt is disabled.
1 = the Load Overrun Interrupt is enabled.
• CPAS: RA Compare
0 = the RA Compare Interrupt is disabled.
1 = the RA Compare Interrupt is enabled.
• CPBS: RB Compare
0 = the RB Compare Interrupt is disabled.
1 = the RB Compare Interrupt is enabled.
• CPCS: RC Compare
0 = the RC Compare Interrupt is disabled.
1 = the RC Compare Interrupt is enabled.
• LDRAS: RA Loading
0 = the Load RA Interrupt is disabled.
1 = the Load RA Interrupt is enabled.
• LDRBS: RB Loading
0 = the Load RB Interrupt is disabled.
1 = the Load RB Interrupt is enabled.
• ETRGS: External Trigger
0 = the External Trigger Interrupt is disabled.
1 = the External Trigger Interrupt is enabled.
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
ETRGS
31
23
15
7
TC Interrupt Mask Register
LDRBS
30
22
14
TC_IMRx [x=0..2]
0x4001002C (0)[0], 0x4001006C (0)[1], 0x400100AC (0)[2], 0x4001402C (1)[0], 0x4001406C (1)[1],
0x400140AC (1)[2]
Read-only
6
LDRAS
29
21
13
5
CPCS
28
20
12
4
CPBS
27
19
11
3
CPAS
26
18
10
2
LOVRS
SAM3S8/SD8
SAM3S8/SD8
25
17
9
1
COVFS
24
16
8
0
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