SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 876

• Manufacturer Part Number: SAM3SD8C
• Manufacturer: Atmel Corporation

35.6
35.6.1
876
876
Functional Description
SAM3S8/SD8
SAM3S8/SD8
PWM Clock Generator
The
Figure 35-2. Functional View of the Clock Generator Block Diagram
The PWM master clock (MCK) is divided in the clock generator module to provide different
clocks available for all channels. Each channel can independently select one of the divided
clocks.
The clock generator is divided in three blocks:
• Clocked by the master clock (MCK), the clock generator module provides 13 clocks.
• Each channel can independently choose one of the clock generator outputs.
• Each channel generates an output waveform with attributes that can be defined
independently for each channel through the user interface registers.
PWM
– a modulo n counter which provides 11 clocks: F
– two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and
F
clkB
MCK
macrocell is primarily composed of a clock generator module and
/16, F
MCK
/32, F
MCK
MCK
/64, F
modulo n counter
MCK
/128, F
MCK
PREA
PREB
/256, F
PWM_MR
PWM_MR
Divider A
Divider B
MCK
DIVA
DIVB
MCK
, F
MCK
MCK/2
MCK/4
MCK/8
MCK/16
MCK/32
MCK/64
MCK/128
MCK/256
MCK/512
MCK/1024
MCK
/512, F
/2, F
clkA
clkB
MCK
MCK
/1024
/4, F
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
4
MCK
channels.
/8,