SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 56

• Manufacturer Part Number: SAM3SD8C
• Manufacturer: Atmel Corporation

10.4.3
56
56
SAM3S8/SD8
SAM3S8/SD8
Behavior of memory accesses
Where:
- Means that the memory system does not guarantee the ordering of the accesses.
< Means that accesses are observed in program order, that is, A1 is always observed before A2.
The behavior of accesses to each region in the memory map is:
Table 10-4.
Note:
The Code, SRAM, and external RAM regions can hold programs. However, ARM recommends
that programs always use the Code region. This is because the processor has separate buses
that enable instruction fetches and data accesses to occur simultaneously.
The MPU can override the default memory access behavior described in this section. For more
information, see
Address
range
0x00000000-
0x1FFFFFFF
0x20000000-
0x3FFFFFFF
0x40000000-
0x5FFFFFFF
0x60000000-
0x9FFFFFFF
0xA0000000-
0xDFFFFFFF
0xE0000000-
0xE00FFFFF
0xE0100000-
0xFFFFFFFF
1. See
Memory access behavior
Memory
region
Code
SRAM
Peripheral
External
RAM
External
device
Private
Peripheral
Bus
Reserved
“Memory regions, types and attributes” on page 54
“Memory protection unit” on page
Memory
type
Normal
Normal
Device
Normal
Device
Strongly-
ordered
Device
(1)
(1)
(1)
(1)
(1)
(1)
(1)
XN
-
-
XN
-
XN
XN
XN
Description
Executable region for program code. You can also put
data here.
Executable region for data. You can also put code
here.
This region includes bit band and bit band alias areas,
see
This region includes bit band and bit band alias areas,
see
Executable region for data.
External Device memory
This region includes the NVIC, System timer, and
system control block.
Reserved
Table 10-6 on page
Table 10-6 on page
196.
for more information.
59.
59.
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12