SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 445

• Manufacturer Part Number: SAM3SD8C
• Manufacturer: Atmel Corporation

25.0.6
25.0.6.1
445
445
SAM3S8/SD8
SAM3S8/SD8
Divider and PLL Block
Divider and Phase Lock Loop Programming
16 periods of Slow Clock, so that the frequency of the 4/8/12 MHz Fast RC oscillator or 3 to 20
MHz Crystal or Ceramic Resonator-based oscillator can be determined.
The device features two Divider/PLL Blocks that permit a wide range of frequencies to be
selected on either the master clock, the processor clock or the programmable clock outputs.
Additionally, they provide a 48 MHz signal to the embedded USB device port regardless of the
frequency of the main clock.
Figure 25-4
Figure 25-4. Dividers and PLL Blocks Diagram
The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the
output of the corresponding divider and the PLL output is a continuous signal at level 0. On
reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0.
The PLL (PLLA, PLLB) allows multiplication of the divider’s outputs. The PLL clock signal has a
frequency that depends on the respective source signal frequency and on the parameters DIV
(DIVA, DIVB) and MUL (MULA, MULB). The factor applied to the source signal frequency is
(MUL + 1)/DIV. When MUL is written to 0, the PLL is disabled and its power consumption is
saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field.
MAINCK
shows the block diagram of the dividers and PLL blocks.
SLCK
Divider B
Divider A
DIVB
DIVA
MULB
MULA
PLLBCOUNT
PLLACOUNT
PLLADIV2
PLLBDIV2
Counter
Counter
PLL B
PLL A
PLL B
PLL A
OUTB
OUTA
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
LOCKB
LOCKA
PLLBCK
PLLACK