ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 54

• Manufacturer Part Number: ATxmega128A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.13.2
5.13.3
5.13.4
8077H–AVR–12/09
INTFLAGS - DMA Interrupt Status Register
STATUS - DMA Status Register
TEMPH - DMA Temporary Register High
• Bit 7:4 - CHnERRIF[3:0]: DMA Channel n Error Interrupt Flag
If an error condition is detected on DMA channel n, the CHnERRIF flag will be set. Writing a one
to this bit location will clear the flag.
• Bit 3:0 - CHnTRNFIF[3:0]: DMA Channel n Transaction Complete Interrupt Flag
When a transaction on channel n has been completed, the CHnTRFIF flag will set. If unlimited
repeat count is enabled, this flag is read as one after each block transfer. Writing a one to this bit
location will clear the flag.
• Bit 7:4 - CHnBUSY[3:0]: DMA Channel Busy
When channel n starts a DMA transaction, the CHnBUSY flag will be read as one. This flag is
automatically cleared when the DMA channel is disabled, when the Channel n transaction Com-
plete Interrupt Flag is set or if the DMA Channel n Error Interrupt flag is set.
• Bit 3:0 - CHnPEND[3:0]: DMA Channel Pending
If a block transfer is pending on DMA channel n, the CHnPEND flag will be read as one. This
flag is automatically cleared when the block transfer starts, or if the transfer is aborted.
• Bit 7:0 - TEMP[7:0]: DMA Temporary Register
This register is used when reading and writing 24-bit registers in the DMA controller. Byte 2 of
the 24-bit register is stored when it is written by the CPU. Byte 2 of the 24-bit register is stored
here when byte 1 is read by the CPU. This register can also be read and written from the user
software.
Reading and writing 24-bit register requires special attention, for details refer to
”Accessing 16-bits Registers” on page
Bit
+0x04
Read/Write
Initial Value
Bit
+0x05
Read/Write
Initial Value
Bit
+0x07
Read/Write
Initial Value
CH3ERRIF
CH3BUSY
R/W
7
0
R/W
7
R
0
7
0
CH2ERRIF
CH2BUSY
R/W
6
0
R/W
R
6
0
6
0
CH1ERRIF
CH1BUSY
R/W
5
0
R/W
R
5
0
5
0
CH0ERRIF
12.
R/W
CH0BUSY
4
0
R/W
R
4
0
4
0
DMTEMP[15:8]
CH3TRNFIF
CH3PEND
R/W
3
0
R/W
R
3
0
3
0
CH2TRNFIF
CH2PEND
R/W
2
0
R/W
R
2
0
2
0
CH1TRNFIF
CH1PEND
R/W
R/W
1
0
R
1
0
1
0
XMEGA A
CH0TRNFIF
CH0PEND
R/W
R/W
0
0
R
0
0
0
0
Section 3.11
INTFLAGS
STATUS
TEMPH
54