ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 341

• Manufacturer Part Number: ATxmega128A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.4.7
28.5
Figure 28-2. JTAG data register overview
28.5.1
8077H–AVR–12/09
Data registers
PDICOM; 0x7
Bypass register
D
D
D
D
D
D
D
D
D
I/O P O R T S
D
P D I
PDICO is an AVR specific instruction and using the JTAG TAP as an alternative interface
towards the PDI (Programming and Debug Interface).
The active states are:
The supported data registers that can be connected between TDI and TDO are:
The Bypass Register consists of a single Shift Register stage. When the Bypass Register is
selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR
controller state. The Bypass Register can be used to shorten the scan chain on a system when
the other devices are to be tested.
D
• Capture-DR: Loads a logical "0" into the Bypass Register.
• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
• Capture-DR: Parallel data from the PDI is sampled into the PDICOM data register.
• Shift-DR: The PDICOM data register is shifted by the TCK input.
• Update-DR: Commands or operands are parallel-latched from the PDICOM data register into
• Bypass register (Ref: register A in
• Device Identification register (Ref: registers C in
• Boundary-scan chain (Ref: register D in
• PDICOM data register (Ref: register B in
the PDI.
J T A G
A
B
C
In te rn a l re g is te rs
B
C
Figure 28-2 on page
C
Figure 28-2 on page
Figure 28-2 on page
B
C T R L
T A P
C
Figure 28-2 on page
341).
341).
341)
to a ll T C K
re g is te rs
341).
XMEGA A
T M S
T C K
T D O
T D I
341