ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 143
ATxmega128A1
Manufacturer Part Number
ATxmega128A1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A1
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
78
Ext Interrupts
78
Usb Speed
No
Usb Interface
No
Spi
12
Twi (i2c)
4
Uart
8
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
8
Output Compare Channels
24
Input Capture Channels
24
Pwm Channels
24
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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13.15 Register Description – Multiport Configuration
13.15.1
13.15.2
8077H–AVR–12/09
MPCMASK - Multi-pin Configuration Mask Register
VPCTRLA - Virtual Port-map Control Register A
• Bit 2:0 - ISC[2:0]: Input/Sense Configuration
These bits set the input and sense configuration on pin n according to
configuration decides how the pin can trigger port interrupts and events. When the input buffer is
not disabled, the schmitt triggered input is sampled (synchronized) and can be read in the IN
register.
Table 13-5.
Note:
• Bit 7:0 - MPCMASK[7:0]: Multi-pin Configuration Mask
The MPCMASK register enables several pins in a port to be configured at the same time. Writing
a one to bit n allows that pin to be part of the multi-pin configuration. When a pin configuration is
written to one of the PINnCTRL registers of the port, that value is written to all the PINnCTRL
registers of the pins matching the bit pattern in the MPCMASK register for that port. It is not nec-
essary to write to one of the registers that is set by the MPCMASK register. The MPCMASK
register is automatically cleared after any PINnCTRL registers is written.
Bit
+0x00
Read/Write
Initial Value
Bit
+0x02
Read/Write
Initial Value
ISC[2:0]
000
001
010
011
100
101
110
111
1. A low pin value will not generate events, and a high pin value will continuously generate
2. Only Port A - F supports the input buffer disable option.
events.
R/W
R/W
7
0
7
0
Input/Sense Configuration
Group Configuration
BOTHEDGES
RISING
FALLING
LEVEL
INTPUT_DISABLE
R/W
R/W
6
0
6
0
VP1MAP[3:0]
R/W
R/W
5
0
5
0
R/W
R/W
4
0
4
0
MPCMASK[7:0]
Sense both edges
Sense rising edge
Sense falling edge
Sense low level
Reserved
Reserved
Reserved
Input buffer disabled
R/W
R/W
3
0
3
0
(1)
R/W
R/W
2
0
2
0
VP0MAP[3:0]
(2)
Description
R/W
R/W
1
0
1
0
Table
XMEGA A
13-5. The sense
R/W
R/W
0
0
0
0
MPCMASK
VPCTRLA
143
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