ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 266

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ATxmega128A1

Manufacturer Part Number
ATxmega128A1
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega128A1

Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
78
Ext Interrupts
78
Usb Speed
No
Usb Interface
No
Spi
12
Twi (i2c)
4
Uart
8
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
8
Output Compare Channels
24
Input Capture Channels
24
Pwm Channels
24
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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23.5.4
23.5.5
8077H–AVR–12/09
KEY - AES Key Register
INTCTRL - AES Interrupt Control Register
The Key Register is used to access the Key memory. Before encryption/decryption can take
place the Key memory must be written sequentially byte by byte through the Key Register. After
encryption/decryption is done the last subkey can be read sequentially byte by byte through the
Key Register.
Loading the initial data to the Key Register should be made after setting the appropriate AES-
mode and direction.
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
These bits enable the AES Interrupt and select the interrupt level as described in
”Interrupts and Programmable Multi-level Interrupt Controller” on page
rupt will be triggered when the SRIF in the STATUS register is set.
Bit
+0x04
Read/Write
Initial Value
Bit
+0x03
Read/Write
Initial Value
• Bit 7:2 - Reserved
• Bit 1:0 - INTLVL[1:0]: AES Interrupt priority and enable
R/W
7
R
0
-
7
0
R/W
R
6
0
-
6
0
R/W
R
5
0
-
5
0
R/W
R
4
0
-
4
0
KEY
R/W
R
3
0
-
3
0
R/W
2
R
0
-
2
0
R/W
R/W
1
0
1
0
INTLVL[1:0]
123. The enabled inter-
XMEGA A
R/W
R/W
0
0
0
0
Section 12.
INTCTRL
KEY
266

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