ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 44

• Manufacturer Part Number: ATxmega128A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

4.20.6
4.20.7
8077H–AVR–12/09
MCUCR – MCU Control Register
EVSYSLOCK – Event System Lock Register
• Bit 7:0 - JTAGUID[7:0]: JTAG User ID
The JTAGUID can be used to identify two devices with identical Device ID in a JTAG scan chain.
The JTAGUID will during reset automatically be loaded from flash and placed in these registers.
• Bit 7:1 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 0 - JTAGD: JTAG Disable
Setting this bit will disable the JTAG interface. This bit is protected by the Configuration Change
Protection mechanism, for details refer to
page
• Bit 7:5 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 4 - EVSYS1LOCK:
Setting this bit will lock all registers in the Event System related to event channels 4 to 7 for fur-
ther modifications. The following registers in the Event System are locked: CH4MUX,
CH4CTRL, CH5MUX, CH5CTRL, CH6MUX, CH6CTRL, CH7MUX, CH7CTRL. This bit is pro-
tected by the Configuration Change Protection mechanism, for details refer to
”Configuration Change Protection” on page
• Bit 3:1 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 0 - EVSYS0LOCK:
Setting this bit will lock all registers in the Event System related to event channels 0 to 3 for fur-
ther modifications. The following registers in the Event System are locked: CH0MUX,
CH0CTRL, CH1MUX, CH1CTRL, CH2MUX, CH2CTRL, CH3MUX, CH3CTRL. This bit is pro-
Bit
+0x06
Read/Write
Initial Value
Bit
+0x08
Read/Write
Initial Value
12.
7
–
R
0
R
7
0
-
R
6
–
0
R
6
0
-
R
5
–
0
R
5
0
-
EVSYS1LOCK
R/W
4
0
Section 3.12 ”Configuration Change Protection” on
R
4
0
-
12.
R
3
–
0
R
3
0
-
R
2
–
0
2
R
0
-
R
1
–
0
R
1
0
-
EVSYS0LOCK
R/W
0
0
XMEGA A
JTAGD
R/W
0
0
Section 3.12
EVSYS_LOCK
MCUCR
44