ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 231

• Manufacturer Part Number: ATxmega128A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.5
8077H–AVR–12/09
Data Modes
As the SS pin is used to signal start and end of transfer, it is also useful for doing packet/byte
synchronization, keeping the Slave bit counter synchronous with the Master clock generator.
There are four combinations of SCK phase and polarity with respect to serial data. The SPI data
transfer formats are shown in
edges of the SCK signal, ensuring sufficient time for data signals to stabilize.
Table 20-2.
Leading edge is the first clock edge in a clock cycle. Trailing edge is the last clock edge in a
clock cycle.
Figure 20-2. SPI Transfer modes
Mode
Mode 0
Mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
Mode 1
Mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
SS
0
1
2
3
MSB first (DORD = 0)
LSB first (DORD = 1)
MSB first (DORD = 0)
LSB first (DORD = 1)
SPI Modes
MSB
LSB
Figure
MSB
LSB
Bit 6
Bit 1
Rising, Sample
Leading Edge
Falling,Sample
20-2. Data bits are shifted out and latched in on opposite
Falling, Setup
Rising, Setup
Bit 6
Bit 1
Bit 5
Bit 2
Bit 5
Bit 2
Bit 4
Bit 3
Bit 4
Bit 3
Bit 3
Bit 4
Bit 3
Bit 4
Bit 2
Bit 5
Bit 2
Bit 5
Bit 1
Bit 6
Falling, Sample
Rising, Sample
Trailing Edge
Falling, Setup
Rising, Setup
Bit 1
Bit 6
LSB
MSB
XMEGA A
LSB
MSB
231