ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 280
ATxmega128A1
Manufacturer Part Number
ATxmega128A1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A1
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
78
Ext Interrupts
78
Usb Speed
No
Usb Interface
No
Spi
12
Twi (i2c)
4
Uart
8
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
8
Output Compare Channels
24
Input Capture Channels
24
Pwm Channels
24
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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24.11.2
8077H–AVR–12/09
SDRAMCTRLA - SDRAM Control Register A
• Bit 1:0 - IFMODE[1:0]: EBI Interface Mode
These bits select EBI interface mode and the number of ports that should be enabled and over-
ridden for EBI, according to
Table 24-9.
• Bit 7:4 - Reserved
These bits are reserved and will always be read as zero.
• Bit 3 - SDCAS: SDRAM CAS Latency
This bit sets the CAS latency as a number of Peripheral 2x Clock cycles. By default this bit is
zero and the CAS latency is two Peripheral 2x Clock cycles. When this bit is set to one the CAS
latency is three Peripheral 2x Clock cycles.
• Bit 2 - SDROW: SDRAM Row Bits
This bit sets the number of row bit used for the connected SDRAM. By default this bit is zero,
and the row bit setting is set to 11 Row Bits. When this bit is set to one the row bit setting is set
to 12 Row Bits.
• Bit 1:0 - SDCOL[1:0]: SDRAM Column Bits
These bits select the number of column bits that are used for the connected SDRAM according
to
Table 24-10. SDRAM Column Bits
Bit
+0x01
Read/Write
Initial Value
table.Table 24-10 on page
IFMODE[1:0]
SDCOL[1:0]
00
01
10
11
00
01
10
11
R
7
0
EBI Mode
-
R
6
0
-
Group Configuration
DISABLED
3PORT
4PORT
2PORT
Group Configuration
8BIT
9BIT
10BIT
11BIT
Table 24-9 on page
280.
R
5
0
-
R
4
0
-
Description
EBI Disabled
EBI enabled with 3-port interface
EBI enabled with 4-port interface
EBI enabled with 2-port interface
SDCAS
Description
8 Column Bits
9 Column Bits
10 Column Bits
11 Column Bits
R/W
280.
3
0
SDROW
R/W
2
0
R/W
1
0
SDCOL[1:0]
R/W
0
0
XMEGA A
SDRAMCTRLA
280
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