ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 261

• Manufacturer Part Number: ATxmega128A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23.4
8077H–AVR–12/09
AES Crypto Module
Figure 23-1. Register file usage during DES encryption/decryption.
Executing one DES instruction performs one round in the DES algorithm. Sixteen rounds must
be executed in increasing order to form the correct DES ciphertext or plaintext. Intermediate
results are stored in the register file (R0-R15) after each DES instruction. After sixteen rounds
the key is located in R8-R16 and the encrypted/decrypted ciphertext/plaintext is located in R0-
R7. The instruction's operand (K) determines which round is executed, and the half carry flag (H)
in the CPU Status Register determines whether encryption or decryption is performed. If the half
carry flag is set, decryption is performed and if the flag is cleared, encryption is performed.
For more details on the DES instruction refer to the AVR instruction set manual.
The AES Crypto Module performs encryption and decryption according to the Advanced Encryp-
tion Standard (FIPS-197). The 128-bit key block and 128-bit data block (plaintext or ciphertext)
must be loaded into the Key and State memory in the AES Crypto Module. This is done by writ-
ing the AES Key Register and State register sequentially with 16 bytes.
It is selectable from software whether the module should perform encryption or decryption. It is
also possible to enable XOR mode where all new data loaded to the State key is XOR’ed with
the current data in the State memory.
The AES module uses 375 clock cycles before the encrypted/decrypted ciphertext/plaintext is
available for readout in the State memory.
Register File
R10
R11
R12
R13
R14
R15
R16
R31
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
...
data0
data1
data2
data3
data4
data5
data6
data7
key0
key1
key2
key3
key4
key5
key6
key7
XMEGA A
261