ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 352
ATxmega128A1
Manufacturer Part Number
ATxmega128A1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A1
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
78
Ext Interrupts
78
Usb Speed
No
Usb Interface
No
Spi
12
Twi (i2c)
4
Uart
8
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
8
Output Compare Channels
24
Input Capture Channels
24
Pwm Channels
24
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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29.4.6
29.4.6.1
8077H–AVR–12/09
Serial transmission
Status signalling
Figure 29-12. Changing and sampling data
When data transmission is initiated, a data byte is loaded in parallel into the shift register, and
then serialized by shifting the byte out on TDO. The Parity bit is generated and stitched to the
data byte during transmission. The transmission speed is dictated by the TCK signal.
If the PDI is in TX-mode (as a response to an LD-instruction), and a transmission request from
the PDI Controller is pending when the TAP-controller enters the Capture-DR state, valid data
will be parallel-loaded into the shift-register and a correct Parity bit will be generated and trans-
mitted along with the data byte in the Shift-DR state.
If the PDI is in RX-mode when the TAP-controller enters the Capture-DR state, an EMPTY byte
(0xEB) will be parallel-loaded into the shift-register, and the Parity bit will be set (forcing a parity
error) when data is shifted out in the Shift-DR state. This situation occurs during normal PDI
command - and operand reception.
If the PDI is in TX-mode (as a response to an LD-instruction), but no transmission request from
the PDI Controller is yet pending when the TAP-controller enters the Capture-DR state, a
DELAY byte (0xDB) will be parallel-loaded into the shift-register, and the Parity bit will be set
(forcing a parity error) when data is shifted out in the Shift-DR state. This situation occurs during
data transmission if the data to be transmitted is not yet available.
Figure 29-13 on page 352
a response to the repeated indirect LD instruction. However, in this example the device is not
able to return data bytes faster than one valid byte per two transmitted frames, intermediate
DELAY characters are inserted.
Figure 29-13. Date not ready marking
If a DELAY data frame is transmitted as a response to an LD instruction, the programmer should
interpret this as if the JTAG-interface had no data yet ready for transmission in the previous DR-
Capture state. The proper reaction from the programmer is to initiate repeated transfers until a
valid data byte is received. The LD-instruction is defined to return a specified number of valid
frames, not just a number of frames. Hence if the programmer detects a DELAY Character after
transmitting an LD-instruction, the LD-instruction should not be retransmitted, because the first
LD response would still be pending.
Programmer
External
Commands/data
TD I/TDO
TC K
Device
FRAME 0
shows an uninterrupted flow of data frames from the PDI (Device) as
REP
FRAME 1
CNT
S am ple
LD *(ptr)
FRAME 2
0xDB 1
S am ple
FRAME 0
FRAME 1
D0
P 0xDB 1
S am ple
FRAME 2
XMEGA A
FRAME 3
D1
P
352
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