ATtiny40 Atmel Corporation, ATtiny40 Datasheet - Page 96

• Manufacturer Part Number: ATtiny40
• Manufacturer: Atmel Corporation

Specifications of ATtiny40

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 18
• Ext Interrupts: 18
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

12.10.5
12.10.6
96
ATtiny40
OCR1B – Timer/Counter1 Output Compare Register B
TIMSK – Timer/Counter1 Interrupt Mask Register
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT1L in 8-bit mode and TCNTH in 16-bit mode). A match can be used to gen-
erate an Output Compare interrupt.
In 16-bit mode the OCR1B register contains the high byte of the 16-bit Output Compare Regis-
ter. To ensure that both the high and the low bytes are written simultaneously when the CPU
writes to these registers, the access is performed using an 8-bit temporary high byte register
(TEMP). This temporary register is shared by all the other 16-bit registers. See
isters in 16-bit Mode” on page
• Bit 7 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector
• Bit 6 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bit 5 – OCIE1B: Timer/Counter1 Output Compare Match B Interrupt Enable
When the OCIE1B bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter occurs, i.e., when the OCF1B bit is set in the Timer/Counter
Interrupt Flag Register – TIFR1.
• Bit 4 – OCIE1A: Timer/Counter1 Output Compare Match A Interrupt Enable
When the OCIE1A bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter1 Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the
Timer/Counter 1 Interrupt Flag Register – TIFR1.
• Bit 3 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter 1 Inter-
rupt Flag Register – TIFR1.
Bit
0x21
Read/Write
Initial Value
Bit
0x26
Read/Write
Initial Value
(See “Interrupts” on page
ICIE1
R/W
R/W
7
0
7
0
R/W
R
6
0
6
–
0
90.
OCIE1B
40.) is executed when the ICF1 flag, located in TIFR, is set.
R/W
R/W
5
0
5
0
OCIE1A
R/W
R/W
4
0
4
0
OCR1B[7:0]
TOIE1
R/W
R/W
3
0
3
0
OCIE0B
R/W
R/W
2
0
2
0
OCIE0A
R/W
R/W
1
0
1
0
“Accessing Reg-
TOIE0
R/W
R/W
0
0
0
0
8263A–AVR–08/10
OCR1B
TIMSK