ATtiny40 Atmel Corporation, ATtiny40 Datasheet - Page 45

• Manufacturer Part Number: ATtiny40
• Manufacturer: Atmel Corporation

Specifications of ATtiny40

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 18
• Ext Interrupts: 18
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

9.3.4
9.3.5
9.3.6
8263A–AVR–08/10
PCMSK2 – Pin Change Mask Register 2
PCMSK1 – Pin Change Mask Register 1
PCMSK0 – Pin Change Mask Register 0
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
• Bits 7:6 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bits 5:0 – PCINT[17:12]: Pin Change Enable Mask 17:12
Each PCINT[17:12] bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT[17:12] is set and the PCIE2 bit in GIMSK is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT[17:12] is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
• Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bits 3:0 – PCINT[11:8]: Pin Change Enable Mask 11:8
Each PCINT[11:8] bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT[11:8] is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT[11:8] is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
• Bits 7:0 – PCINT[7:0]: Pin Change Enable Mask 7:0
Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT[7:0] is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT[7:0] is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
Bit
0x1A
Read/Write
Initial Value
Bit
0x0A
Read/Write
Initial Value
Bit
0x09
Read/Write
Initial Value
PCINT7
R/W
R
7
–
0
R
7
–
0
7
0
PCINT6
R
R/W
6
–
0
R
6
–
0
6
0
PCINT17
PCINT5
R
5
–
0
R/W
R/W
5
0
5
0
PCINT16
PCINT4
R
4
–
0
R/W
R/W
4
0
4
0
PCINT11
PCINT15
R/W
PCINT3
3
0
R/W
R/W
3
0
3
0
PCINT10
PCINT14
PCINT2
R/W
R/W
R/W
2
0
2
0
2
0
PCINT13
PCINT9
PCINT1
R/W
R/W
R/W
1
0
1
0
1
0
PCINT12
PCINT0
PCINT8
R/W
R/W
R/W
0
0
0
0
0
0
PCMSK2
PCMSK1
PCMSK0
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