ATtiny40 Atmel Corporation, ATtiny40 Datasheet - Page 139

• Manufacturer Part Number: ATtiny40
• Manufacturer: Atmel Corporation

Specifications of ATtiny40

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 18
• Ext Interrupts: 18
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

17.4.1.3
17.4.1.4
17.4.2
17.4.3
17.5
17.5.1
8263A–AVR–08/10
Register Description
Receiving Data Packets
Transmitting Data Packets
TWSCRA – TWI Slave Control Register A
Case 3: Collision
Case 4: STOP condition received.
received. Data, Repeated START or STOP can be received after this. If NACK is indicated the
slave will wait for a new START condition and address match.
If the slave is not able to send a high level or NACK, the Collision flag is set and it will disable the
data and acknowledge output from the slave logic. The clock hold is released. A START or
repeated START condition will be accepted.
Operation is the same as case 1 or 2 above with one exception. When the STOP condition is
received, the Slave Address/Stop flag will be set indicating that a STOP condition and not an
address match occurred.
The slave will know when an address packet with R/W direction bit cleared has been success-
fully received. After acknowledging this, the slave must be ready to receive data. When a data
packet is received the Data Interrupt Flag is set, and the slave must indicate ACK or NACK.
After indicating a NACK, the slave must expect a STOP or Repeated START condition.
The slave will know when an address packet, with R/W direction bit set, has been successfully
received. It can then start sending data by writing to the Slave Data register. When a data packet
transmission is completed, the Data Interrupt Flag is set. If the master indicates NACK, the slave
must stop transmitting data, and expect a STOP or Repeated START condition.
• Bit 7 – TWSHE: TWI SDA Hold Time Enable
When this bit is set the internal hold time on SDA with respect to the negative edge on SCL is
enabled.
• Bit 6 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bit 5 – TWDIE: TWI Data Interrupt Enable
When this bit is set and interrupts are enabled, a TWI interrupt will be generated when the data
interrupt flag (TWDIF) in TWSSRA is set.
• Bit 4 – TWASIE: TWI Address/Stop Interrupt Enable
When this bit is set and interrupts are enabled, a TWI interrupt will be generated when the
address/stop interrupt flag (TWASIF) in TWSSRA is set.
• Bit 3 – TWEN: Two-Wire Interface Enable
When this bit is set the slave Two-Wire Interface is enabled.
Bit
0x2D
Read/Write
Initial Value
TWSHE
R/W
7
0
R
6
–
0
TWDIE
R/W
5
0
TWASIE
R/W
4
0
TWEN
R/W
3
0
TWSIE
R/W
2
0
TWPME
R/W
1
0
TWSME
R/W
0
0
TWSCRA
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