ATtiny40 Atmel Corporation, ATtiny40 Datasheet - Page 63

• Manufacturer Part Number: ATtiny40
• Manufacturer: Atmel Corporation

Specifications of ATtiny40

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 18
• Ext Interrupts: 18
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

10.4.2
10.4.3
10.4.4
10.4.5
10.4.6
10.4.7
10.4.8
8263A–AVR–08/10
PUEA – Port A Pull-up Enable Control Register
PORTA – Port A Data Register
DDRA – Port A Data Direction Register
PINA – Port A Input Pins
PUEB – Port B Pull-up Enable Control Register
PORTB – Port B Data Register
DDRB – Port B Data Direction Register
• Bit 0 – BBMA: Break-Before-Make Mode Enable
When this bit is set the Break-Before-Make mode is activated for the entire Port A. The interme-
diate tri-state cycle is then inserted when writing DDRAn to make an output. For further
information, see
Bit
0x03
Read/Write
Initial Value
Bit
0x02
Read/Write
Initial Value
Bit
0x01
Read/Write
Initial Value
Bit
0x00
Read/Write
Initial Value
Bit
0x07
Read/Write
Initial Value
Bit
0x06
Read/Write
Initial Value
Bit
0x05
Read/Write
Initial Value
PORTA7
PUEA7
PINA7
DDA7
R/W
R/W
R/W
R/W
N/A
R
R
R
7
0
7
0
7
0
7
7
–
0
7
–
0
7
–
0
“Break-Before-Make Switching” on page
PORTA6
PUEA6
PINA6
DDA6
R/W
R/W
R/W
R/W
N/A
R
R
R
6
0
6
0
6
0
6
6
–
0
6
–
0
6
–
0
PORTA5
PUEA5
PINA5
DDA5
R/W
R/W
R/W
R/W
N/A
R
R
5
0
5
0
5
R
5
–
0
5
–
0
5
0
5
–
0
PORTA4
PUEA4
PINA4
DDA4
R/W
R/W
R/W
R/W
N/A
R
R
4
0
4
0
4
R
4
–
0
4
–
0
4
0
4
–
0
PORTB3
PORTA3
PUEA3
PUEB3
PINA3
DDA3
DDB3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
N/A
3
0
3
0
3
3
0
3
0
3
0
3
0
48.
PORTB2
PORTA2
PUEA2
PUEB2
PINA2
DDA2
DDB2
R/W
R/W
R/W
R/W
R/W
R/W
N/A
R/W
2
2
0
2
0
2
0
2
0
2
0
2
0
PORTB1
PORTA1
PUEA1
PUEB1
PINA1
DDA1
DDB1
R/W
R/W
R/W
R/W
R/W
R/W
N/A
R/W
1
1
0
1
0
1
0
1
0
1
0
1
0
PORTB0
PORTA0
PUEA0
PINA0
PUEB0
DDA0
DDB0
R/W
R/W
R/W
R/W
R/W
R/W
N/A
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
PORTA
PORTB
DDRA
DDRB
PUEA
PINA
PUEB
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