ATtiny40 Atmel Corporation, ATtiny40 Datasheet - Page 89
ATtiny40
Manufacturer Part Number
ATtiny40
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny40
Flash (kbytes)
4 Kbytes
Pin Count
20
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
Yes
Max I/o Pins
18
Ext Interrupts
18
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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12.7.3
12.7.4
12.7.5
12.8
8263A–AVR–08/10
Timer/Counter Timing Diagrams
Normal, 16-bit Mode
8-bit Input Capture Mode
16-bit Input Capture Mode
its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can
occur. As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle
that the counter counts from MAX to 0x00.
In 16-bit mode, see
overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the
bottom (0x0000). The Overflow Flag (TOV1) will be set in the same timer clock cycle as the
TCNT1H/L becomes zero. The TOV1 Flag in this case behaves like a 17th bit, except that it is
only set, not cleared. However, combined with the timer overflow interrupt that automatically
clears the TOV1 Flag, the timer resolution can be increased by software. There are no special
cases to consider in the Normal mode, a new counter value can be written anytime. The Output
Compare Unit can be used to generate interrupts at some given time.
The Timer/Counter1 can also be used in an 8-bit Input Capture mode, see
88
The Timer/Counter1 can also be used in a 16-bit Input Capture mode, see
88
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set.
shows the count sequence close to the MAX value.
Figure 12-5. Timer/Counter Timing Diagram, no Prescaling
Figure 12-6
TCNTn
(clk
TOVn
clk
clk
for bit settings. For full description, see the section
for bit settings. For full description, see the section
I/O
I/O
Tn
/1)
shows the same timing data, but with the prescaler enabled.
Figure 12-5
Table 12-3 on page
MAX - 1
contains timing data for basic Timer/Counter operation. The figure
88, the counter (TCNT1H/L) is a incrementing until it
MAX
“Input Capture Unit” on page
“Input Capture Unit” on page
BOTTOM
T1
) is therefore shown as a
Table 12-3 on page
Table 12-3 on page
BOTTOM + 1
85.
85.
89
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