ATtiny40 Atmel Corporation, ATtiny40 Datasheet - Page 141

• Manufacturer Part Number: ATtiny40
• Manufacturer: Atmel Corporation

Specifications of ATtiny40

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 18
• Ext Interrupts: 18
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

17.5.3
8263A–AVR–08/10
TWSSRA – TWI Slave Status Register A
Table 17-2.
Writing the TWCMD bits will automatically release the SCL line and clear the TWCH and slave
interrupt flags.
TWAA and TWCMDn bits can be written at the same time. Acknowledge Action will then be exe-
cuted before the command is triggered.
The TWCMDn bits are strobed and always read zero.
• Bit 7 – TWDIF: TWI Data Interrupt Flag
This flag is set when a data byte has been successfully received, i.e. no bus errors or collisions
have occurred during the operation. When this flag is set the slave forces the SCL line low,
stretching the TWI clock period. The SCL line is released by clearing the interrupt flags.
Writing a one to this bit will clear the flag. This flag is also automatically cleared when writing a
valid command to the TWCMDn bits in TWSCRB.
• Bit 6 – TWASIF: TWI Address/Stop Interrupt Flag
This flag is set when the slave detects that a valid address has been received, or when a trans-
mit collision has been detected. When this flag is set the slave forces the SCL line low,
stretching the TWI clock period. The SCL line is released by clearing the interrupt flags.
If TWASIE in TWSCRA is set, a STOP condition on the bus will also set TWASIF. STOP condi-
tion will set the flag only if system clock is faster than the minimum bus free time between STOP
and START.
Writing a one to this bit will clear the flag. This flag is also automatically cleared when writing a
valid command to the TWCMDn bits in TWSCRB.
Bit
0x2B
Read/Write
Initial Value
TWCMD[1:0]
00
01
10
11
TWI Slave Command
TWDIF
R/W
Used to complete transaction
Used in response to an Address Byte (TWASIF is set)
Used in response to a Data Byte (TWDIF is set)
7
0
TWDIR
X
X
0
1
0
1
0
1
TWASIF
R/W
6
0
Operation
No action
Reserved
Execute Acknowledge Action, then wait for any START (S/Sr) condition
Wait for any START (S/Sr) condition
Execute Acknowledge Action, then receive next byte
Execute Acknowledge Action, then set TWDIF
Execute Acknowledge Action, then wait for next byte
No action
TWCH
R
5
0
TWRA
R
4
0
TWC
R/W
3
0
TWBE
R/W
2
0
TWDIR
R/W
1
0
TWAS
R/W
0
0
TWSCRA
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