ATtiny40 Atmel Corporation, ATtiny40 Datasheet - Page 13

no-image

ATtiny40

Manufacturer Part Number
ATtiny40
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATtiny40

Flash (kbytes)
4 Kbytes
Pin Count
20
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
Yes
Max I/o Pins
18
Ext Interrupts
18
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATtiny40-MMHR
Quantity:
6 000
4.8
4.8.1
4.8.2
8263A–AVR–08/10
Register Description
CCP – Configuration Change Protection Register
SPH and SPL – Stack Pointer Register
• Bits 7:0 – CCP[7:0]: Configuration Change Protection
In order to change the contents of a protected I/O register the CCP register must first be written
with the correct signature. After CCP is written the protected I/O registers may be written to dur-
ing the next four CPU instruction cycles. All interrupts are ignored during these cycles. After
these cycles interrupts are automatically handled again by the CPU, and any pending interrupts
will be executed according to their priority.
When the protected I/O register signature is written, CCP0 will read as one as long as the pro-
tected feature is enabled, while CCP[7:1] will always read as zero.
Table 4-1
Table 4-1.
Notes:
• Bits 15:0 – SP[15:0]: Stack Pointer
The Stack Pointer register points to the top of the stack, which is implemented as growing from
higher memory locations to lower memory locations. Hence, a stack PUSH command decreases
the Stack Pointer. The stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled.
The Stack Pointer in ATtiny40 is implemented as two 8-bit registers in the I/O space.
Bit
0x3C
Read/Write
Initial Value
Bit
0x3E
0x3D
Read/Write
Read/Write
Initial Value
Initial Value
Signature
0xD8
1. Only WDE and WDP[3:0] bits are protected in WDTCSR.
2. Only BODS bit is protected in MCUCR.
shows the signatures that are in recognised.
Signatures Recognised by the Configuration Change Protection Register
RAMEND
RAMEND
SP15
R/W
SP7
Group
IOREG: CLKMSR, CLKPSR, WDTCSR
W
7
0
15
R
7
RAMEND
RAMEND
SP14
SP6
R/W
W
6
0
14
R
6
RAMEND
RAMEND
SP13
SP5
R/W
W
5
0
13
R
5
RAMEND
RAMEND
SP12
SP4
R/W
W
4
0
12
R
4
CCP[7:0]
RAMEND
RAMEND
(1)
SP11
SP3
R/W
W
3
0
11
, MCUCR
R
3
RAMEND
RAMEND
SP10
SP2
R/W
W
(2)
2
0
10
R
2
Description
Protected I/O register
RAMEND
RAMEND
SP9
SP1
R/W
W
1
0
R
9
1
RAMEND
RAMEND
R/W
SP8
SP0
W
0
0
R
8
0
CCP
SPH
SPL
13

Related parts for ATtiny40