ATtiny40 Atmel Corporation, ATtiny40 Datasheet - Page 30

• Manufacturer Part Number: ATtiny40
• Manufacturer: Atmel Corporation

Specifications of ATtiny40

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 18
• Ext Interrupts: 18
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

7.5
7.5.1
30
Register Description
ATtiny40
MCUCR – MCU Control Register
buffer is enabled and the input signal is left floating or has an analog signal level close to V
the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V
input buffers can be disabled by writing to the Digital Input Disable Register (DIDR0). Refer to
“DIDR0 – Digital Input Disable Register 0” on page 104
The MCU Control Register contains bits for controlling external interrupt sensing and power
management.
• Bit 5 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bit 4 – BODS: BOD Sleep
In order to disable BOD during sleep (see
logic one. This is controlled by a protected change sequence, as follows:
A sleep instruction must be executed while BODS is active in order to turn off the BOD for the
actual sleep mode.
The BODS bit is automatically cleared when the device wakes up. Alternatively the BODS bit
can be cleared by writing logic zero to it. This does not require protected sequence.
• Bits 3:1 – SM[2:0]: Sleep Mode Select Bits 2, 1 and 0
These bits select between available sleep modes, as shown in
Table 7-2.
Bit
0x3A
Read/Write
Initial Value
1. Write the signature for change enable of protected I/O registers to register CCP.
2. Within four instruction cycles write the BODS bit.
SM2
0
0
0
0
1
1
1
1
ISC01
Sleep Mode Select
R/W
CC
7
0
/2 on an input pin can cause significant current even in active mode. Digital
SM1
ISC00
0
0
1
1
0
0
1
1
R/W
6
0
R
5
–
0
SM0
0
1
0
1
0
1
0
1
BODS
R/W
0
4
Table 7-1 on page
SM2
R/W
Sleep Mode
Idle
ADC noise reduction
Power-down
Reserved
Standby
Reserved
Reserved
Reserved
3
0
for details.
SM1
R/W
2
0
27) the BODS bit must be written to
Table
SM0
R/W
1
0
7-2.
R/W
SE
0
0
MCUCR
8263A–AVR–08/10
CC
/2,