ATtiny40 Atmel Corporation, ATtiny40 Datasheet - Page 160

• Manufacturer Part Number: ATtiny40
• Manufacturer: Atmel Corporation

Specifications of ATtiny40

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 18
• Ext Interrupts: 18
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

20.4
20.4.1
160
Accessing the NVM
ATtiny40
Addressing the Flash
NVM lock bits, and all Flash memory sections are mapped to the data space as shown in
5-1 on page
in the data space.
The NVM Controller recognises a set of commands that can be used to instruct the controller
what type of programming task to perform on the NVM. Commands to the NVM Controller are
issued via the NVM Command Register. See
Register” on page
writing data to the NVM locations mapped to the data space.
When the NVM Controller is busy performing an operation it will signal this via the NVM Busy
Flag in the NVM Control and Status Register. See
and Status Register” on page
long as the busy flag is active. This is to ensure that the current command is fully executed
before a new command can start.
Programming any part of the NVM will automatically inhibit the following operations:
The ATtiny40 supports only external programming. Internal programming operations to the NVM
have been disabled, which means any internal attempt to write or erase NVM locations will fail.
The data space uses byte accessing but since the Flash sections are accessed as words and
organized in pages, the byte-address of the data space must be converted to the word-address
of the Flash section. This is illustrated in
Figure 20-1. Addressing the Flash Memory
• All programming to any other part of the NVM
• All reading from any NVM location
ADDRESS POINTER
SECTIONEND
16
16. The NVM can be accessed for read and programming via the locations mapped
00
01
02
...
...
...
SECTION
FLASH
164. After the selected command has been loaded, the operation is started by
PAGE
164. The NVM Command Register is blocked for write access as
PADDRMSB
WITHIN A FLASH
PAGE ADDRESS
Figure
SECTION
PADDR
PAGEEND
20-1. Also, see
“NVMCMD – Non-Volatile Memory Command
00
01
...
...
...
“NVMCSR – Non-Volatile Memory Control
WADDRMSB+1
FLASH
WORD
PAGE
Table 20-3 on page
WADDRMSB
WADDR
WORD ADDRESS
WITHIN A FLASH
PAGE
1
0/1
LOW/HIGH
BYTE SELECT
8263A–AVR–08/10
158.
Figure