ATtiny40 Atmel Corporation, ATtiny40 Datasheet - Page 49
ATtiny40
Manufacturer Part Number
ATtiny40
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny40
Flash (kbytes)
4 Kbytes
Pin Count
20
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
Yes
Max I/o Pins
18
Ext Interrupts
18
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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10.2.4
8263A–AVR–08/10
Reading the Pin Value
Figure 10-3. Switching Between Input and Output in Break-Before-Make-Mode
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in
ing latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay.
shows a timing diagram of the synchronization when reading an externally applied pin value.
The maximum and minimum propagation delays are denoted t
Figure 10-4. Synchronization when Reading an Externally Applied Pin value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed
between ½ and 1½ system clock period depending upon the time of assertion.
INSTRUCTIONS
SYSTEM CLK
INSTRUCTIONS
SYSTEM CLK
SYNC LATCH
PORTx
DDRx
Px0
Px1
r16
r17
PINxn
r17
0x01
tri-state
out DDRx, r16
Figure 10-2 on page
XXX
intermediate tri-state cycle
0x02
tri-state
nop
t
pd, max
0x02
0x01
0x55
0x00
XXX
47, the PINxn Register bit and the preced-
out DDRx, r17
t
pd, min
pd,max
in r17, PINx
and t
intermediate tri-state cycle
tri-state
0x01
pd,min
respectively.
0xFF
Figure 10-4
49
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