ATtiny40 Atmel Corporation, ATtiny40 Datasheet - Page 145

• Manufacturer Part Number: ATtiny40
• Manufacturer: Atmel Corporation

Specifications of ATtiny40

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 18
• Ext Interrupts: 18
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

19. Programming Interface
19.1
19.2
19.3
8263A–AVR–08/10
Features
Overview
Physical Layer of Tiny Programming Interface
•
•
The Tiny Programming Interface (TPI) supports external programming of all Non-Volatile Memo-
ries (NVM). Memory programming is done via the NVM Controller, by executing NVM controller
commands as described in
The Tiny Programming Interface (TPI) provides access to the programming facilities. The inter-
face consists of two layers: the access layer and the physical layer. The layers are illustrated in
Figure
Figure 19-1. The Tiny Programming Interface and Related Internal Interfaces
Programming is done via the physical interface. This is a 3-pin interface, which uses the RESET
pin as enable, the TPICLK pin as the clock input, and the TPIDATA pin as data input and output.
NVM can be programmed at 5V, only.
The TPI physical layer handles the basic low-level serial communication. The TPI physical layer
uses a bi-directional, half-duplex serial receiver and transmitter. The physical layer includes
serial-to-parallel and parallel-to-serial data conversion, start-of-frame detection, frame error
detection, parity error detection, parity generation and collision detection.
Physical Layer:
Access Layer:
– Synchronous Data Transfer
– Bi-directional, Half-duplex Receiver And Transmitter
– Fixed Frame Format With One Start Bit, 8 Data Bits, One Parity Bit And 2 Stop Bits
– Parity Error Detection, Frame Error Detection And Break Character Detection
– Parity Generation And Collision Detection
– Automatic Guard Time Insertion Between Data Reception And Transmission
– Communication Based On Messages
– Automatic Exception Handling Mechanism
– Compact Instruction Set
– NVM Programming Access Control
– Tiny Programming Interface Control And Status Space Access Control
– Data Space Access Control
19-1.
TPIDATA
TPICLK
RESET
TINY PROGRAMMING INTERFACE (TPI)
PHYSICAL
LAYER
“Memory Programming” on page
ACCESS
LAYER
156.
DATA BUS
NON-VOLATILE
CONTROLLER
MEMORIES
NVM
145