ATtiny40 Atmel Corporation, ATtiny40 Datasheet - Page 148
ATtiny40
Manufacturer Part Number
ATtiny40
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny40
Flash (kbytes)
4 Kbytes
Pin Count
20
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
Yes
Max I/o Pins
18
Ext Interrupts
18
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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19.3.7
19.3.8
19.3.9
148
ATtiny40
Serial Data Reception
Serial Data Transmission
Collision Detection Exception
Figure 19-5. Data changing and Data sampling.
The TPI physical layer supports two modes of operation: Transmit and Receive. By default, the
layer is in Receive mode, waiting for a start bit. The mode of operation is controlled by the
access layer.
When the TPI physical layer is in receive mode, data reception is started as soon as a start bit
has been detected. Each bit that follows the start bit will be sampled at the rising edge of the
TPICLK and shifted into the shift register until the second stop bit has been received. When the
complete frame is present in the shift register the received data will be available for the TPI
access layer.
There are three possible exceptions in the receive mode: frame error, parity error and break
detection. All these exceptions are signalized to the TPI access layer, which then enters the
error state and puts the TPI physical layer into receive mode, waiting for a BREAK character.
When the TPI physical layer is ready to send a new frame it initiates data transmission by load-
ing the shift register with the data to be transmitted. When the shift register has been loaded with
new data, the transmitter shifts one complete frame out on the TPIDATA line at the transfer rate
given by TPICLK.
If a collision is detected during transmission, the output driver is disabled. The TPI access layer
enters the error state and the TPI physical layer is put into receive mode, waiting for a BREAK
character.
The TPI physical layer uses one bi-directional data line for both data reception and transmission.
A possible drive contention may occur, if the external programmer and the TPI physical layer
drive the TPIDATA line simultaneously. In order to reduce the effect of the drive contention, a
collision detection mechanism is supported. The collision detection is based on the way the TPI
physical layer drives the TPIDATA line.
• Frame Error Exception. The frame error exception indicates the state of the stop bit. The
• Parity Error Exception. The parity of the data bits is calculated during the frame reception.
• Break Detection Exception. The Break detection exception is given when a complete frame
frame error exception is set if the stop bit was read as zero.
After the frame is received completely, the result is compared with the parity bit of the frame.
If the comparison fails the parity error exception is signalized.
of all zeros has been received.
TPICLK
TPIDATA
SAMPLE
SETUP
8263A–AVR–08/10
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