ATtiny40 Atmel Corporation, ATtiny40 Datasheet - Page 77
ATtiny40
Manufacturer Part Number
ATtiny40
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny40
Flash (kbytes)
4 Kbytes
Pin Count
20
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
Yes
Max I/o Pins
18
Ext Interrupts
18
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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8263A–AVR–08/10
Table 11-3.
Note:
Table 11-4
PWM mode.
Table 11-4.
Note:
• Bits 5:4 – COM0B[1:0]: Compare Match Output B Mode
These bits control the Output Compare pin (OC0B) behavior. If one or both of COM0B[1:0] bits
are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected to.
The Data Direction Register (DDR) bit corresponding to the OC0B pin must be set in order to
enable the output driver.
When OC0B is connected to the pin, the function of COM0B[1:0] bits depend on WGM0[2:0] bit
setting.
or CTC mode (non-PWM).
Table 11-5.
COM0A1
COM0A1
COM0B1
0
0
1
1
0
0
1
1
0
0
1
1
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
1. When OCR0A equals TOP and COM0A1 is set, the Compare Match is ignored, but the set or
Table 11-5
pare Match is ignored, but the set or clear is done at BOTTOM. See
page 71
clear is done at TOP. See
shows COM0A[1:0] bit functionality when WGM0[2:0] bits are set to phase correct
Compare Output Mode, Fast PWM Mode
Compare Output Mode, Phase Correct PWM Mode
Compare Output Mode, non-PWM Mode
COM0A0
COM0A0
COM0B0
for more details.
shows COM0B[1:0] bit functionality when WGM0[2:0] bits are set to normal
0
1
0
1
0
1
0
1
0
1
0
1
Description
Normal port operation, OC0A disconnected
WGM02 = 0: Normal Port Operation, OC0A Disconnected
WGM02 = 1: Toggle OC0A on Compare Match
Clear OC0A on Compare Match
Set OC0A at BOTTOM (non-inverting mode)
Set OC0A on Compare Match
Clear OC0A at BOTTOM (inverting mode)
Description
Normal port operation, OC0A disconnected.
WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
Clear OC0A on Compare Match when up-counting. Set OC0A on
Compare Match when down-counting.
Set OC0A on Compare Match when up-counting. Clear OC0A on
Compare Match when down-counting.
Description
Normal port operation, OC0B disconnected.
Toggle OC0B on Compare Match
Clear OC0B on Compare Match
Set OC0B on Compare Match
“Phase Correct PWM Mode” on page 73
(1)
(1)
for more details.
“Fast PWM Mode” on
77
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