ATtiny40 Atmel Corporation, ATtiny40 Datasheet - Page 43

• Manufacturer Part Number: ATtiny40
• Manufacturer: Atmel Corporation

Specifications of ATtiny40

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 18
• Ext Interrupts: 18
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

9.3
9.3.1
9.3.2
8263A–AVR–08/10
Register Description
MCUCR – MCU Control Register
GIMSK – General Interrupt Mask Register
The MCU Control Register contains bits for controlling external interrupt sensing and power
management.
• Bits 7:6 – ISC0[1:0]: Interrupt Sense Control
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate
an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt.
Table 9-2.
• Bit 7 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bit 6 – PCIE2: Pin Change Interrupt Enable 2
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 2 is enabled. Any change on any enabled PCINT[17:12] pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0
Interrupt Vector. PCINT[17:12] pins are enabled individually by the PCMSK2 Register.
• Bit 5 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 1 is enabled. Any change on any enabled PCINT[11:8] pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1
Interrupt Vector. PCINT[11:8] pins are enabled individually by the PCMSK1 Register.
Bit
0x3A
Read/Write
Initial Value
Bit
0x0C
Read/Write
Initial Value
ISC01
0
0
1
1
ISC01
Interrupt 0 Sense Control
R/W
ISC00
7
0
R
7
–
0
0
1
0
1
ISC00
R/W
Table
6
0
PCIE2
R/W
Description
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
6
0
9-2. The value on the INT0 pin is sampled before detecting edges.
R
5
–
0
PCIE1
R/W
5
0
BODS
R/W
4
0
PCIE0
R/W
4
0
SM2
R/W
3
0
R
3
–
0
SM1
R/W
2
0
R
2
–
0
SM0
R/W
1
0
R
1
–
0
R/W
SE
0
0
INT0
MCUCR
R/W
0
0
GIMSK
43